公开(公告)号：US11715685B2

公开(公告)日：2023-08-01

申请号：US17064453

申请日：2020-10-06

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Nancy M. Lomeli ,  Xiao Li

IPC: H01L23/522 ,  G11C16/08 ,  G11C16/24 ,  H01L21/768 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/5226 ,  G11C16/08 ,  G11C16/24 ,  H01L21/76831 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure comprising insulative structures and electrically conductive structures vertically alternating with the insulative structures, pillar structures extending vertically through the stack structure, an etch stop material vertically overlaying the stack structure, and a first dielectric material vertically overlying the etch stop material. The method further includes removing portions of the first dielectric material, the etch stop material, and an upper region of the stack structure to form a trench interposed between horizontally neighboring groups of the pillar structures, forming a liner material within the trench, and substantially filling a remaining portion of the trench with a second dielectric material to form a dielectric barrier structure.

公开(公告)号：US20230209831A1

公开(公告)日：2023-06-29

申请号：US17658778

申请日：2022-04-11

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  Nancy M. Lomeli

IPC: H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11582

Abstract: A microelectronic device includes a source stack, a source contact vertically adjacent to the source stack, a semiconductor material vertically adjacent to the source contact, tiers of alternating conductive materials and dielectric materials vertically adjacent to the semiconductor dielectric material, a dielectric structure within a slot structure and extending through the tiers of the microelectronic device to the source contact of the microelectronic device, oxide cap structures laterally between the semiconductor material and the dielectric structure, and pillars extending through the tiers, the semiconductor material, and the source contact and into the source stack. Related electronic systems and methods are also disclosed.

公开(公告)号：US20230209819A1

公开(公告)日：2023-06-29

申请号：US17655222

申请日：2022-03-17

Applicant: Micron Technology, Inc.

Inventor： Nancy M. Lomeli ,  Jiewei Chen ,  Naiming Liu

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/538

CPC classification number: H01L27/11556 ,  G11C5/025 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/5386

Abstract: A microelectronic device includes a stack structure including insulative structures and conductive structures vertically alternating with the insulative structures. At least one of the insulative structures includes interfacial regions proximate interfaces between the at least one of the insulative structures and two of the conductive structures vertically neighboring the at least one of the insulative structures; and an intermediate region interposed between the interfacial regions. The intermediate region has a different material composition and relatively greater strength than the interfacial regions.

公开(公告)号：US20230170024A1

公开(公告)日：2023-06-01

申请号：US17537990

申请日：2021-11-30

Applicant: Micron Technology, Inc.

Inventor： Nancy M. Lomeli ,  Rajasekhar Venigalla

IPC: G11C16/04 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11582 ,  H01L23/48 ,  H01L27/1157

CPC classification number: G11C16/0483 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11582 ,  H01L23/481 ,  H01L27/1157

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAVs comprise an upper portion directly above and joined with a lower portion. The individual TAVs comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. The lower portion is wider in the vertical cross-section than the upper portion where the upper and lower portions join. Other embodiments, including method, are disclosed.

公开(公告)号：US11659708B2

公开(公告)日：2023-05-23

申请号：US17091420

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H01L27/11582

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprises a conductor tier comprising upper conductor material directly above and directly electrically coupled to lower conductor material. The upper and lower conductor materials comprise different compositions relative one another. Laterally-spaced memory blocks individually comprising a vertical stack comprise alternating insulative tiers and conductive tiers, Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers and through the upper conductor material into the lower conductor material. The channel material of the channel-material strings is directly electrically coupled to the upper and lower conductor materials of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US20230137958A1

公开(公告)日：2023-05-04

申请号：US17517355

申请日：2021-11-02

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Nancy M. Lomeli ,  Rui Zhang

IPC: H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

Abstract: Memory circuitry comprising strings of memory cells comprising laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from the memory-array region into a stair-step region. Individual stairs in the stair-step region comprise one of the conductive tiers and a riser. Conductive vias are individually directly against conductive material that is in the one conductive tier in one of the individual stairs. Individual of the conductive vias where directly against the conductive material are horizontally-longitudinally-elongated at an angle of 0° to 60° horizontally from the riser of the one individual stair. Other embodiments, including method, are disclosed.

公开(公告)号：US11631740B2

公开(公告)日：2023-04-18

申请号：US17097410

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H01L27/11582 ,  H01L29/10 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. A ring is around individual of the channel-material strings in at least one of a lowest of the conductive tiers or a lowest of the insulative tiers. Individual of the rings have a top that is below all of the memory cells. Other embodiments are disclosed.

公开(公告)号：US20230061327A1

公开(公告)日：2023-03-02

申请号：US18047245

申请日：2022-10-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/538 ,  G11C5/06 ,  G11C5/02 ,  H01L27/11575

Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11515320B2

公开(公告)日：2022-11-29

申请号：US17012741

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli

IPC: H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/538 ,  G11C5/06 ,  G11C5/02

Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20220231042A1

公开(公告)日：2022-07-21

申请号：US17150322

申请日：2021-01-15

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H01L27/11582 ,  H01L21/225 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming vertically-extending channel-material strings into a stack comprising vertically-alternating first tiers and second tiers. Material of the first tiers is of different composition from material of the second tiers. A liner is formed laterally-outside of individual of the channel-material strings in one of the first tiers and in one of the second tiers. The liners are isotropically etched to form void-spaces in the one second tier above the one first tier. Individual of the void-spaces are laterally-between the individual channel-material strings and the second-tier material in the one second tier. Conductively-doped semiconductive material is formed against sidewalls of the channel material of the channel-material strings in the one first tier and that extends upwardly into the void-spaces in the one second tier. The conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces. Other aspects, including structure independent of method, are disclosed.