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    Semiconductor structure formation
    41.
    发明授权
    Semiconductor structure formation 有权

    公开(公告)号：US11469103B2

    公开(公告)日：2022-10-11

    申请号：US17153997

    申请日：2021-01-21

    Applicant: Micron Technology, Inc.

    Inventor： Nicholas R. Tapias ,  Sanjeev Sapra ,  Anish A. Khandekar ,  Shen Hu

    IPC: H01L21/02 ,  H01L21/762 ,  H01L21/8238

    Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

    Vertical Transistors
    42.
    发明申请
    Vertical Transistors 有权

    公开(公告)号：US20220181434A1

    公开(公告)日：2022-06-09

    申请号：US17116120

    申请日：2020-12-09

    Applicant: Micron Technology, Inc.

    Inventor： Yi Fang Lee ,  Hung-Wei Liu ,  Ning Lu ,  Anish A. Khandekar ,  Jeffery B. Hull ,  Silvia Borsari

    IPC: H01L29/04 ,  H01L29/786

    Abstract: A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.

    Arrays of elevationally-extending strings of memory cells and methods used in forming an array of elevationally-extending strings of memory cells
    44.
    发明授权
    Arrays of elevationally-extending strings of memory cells and methods used in forming an array of elevationally-extending strings of memory cells 有权

    公开(公告)号：US10665469B2

    公开(公告)日：2020-05-26

    申请号：US16128109

    申请日：2018-09-11

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

    IPC: H01L27/115 ,  H01L21/311 ,  H01L27/11556 ,  H01L21/02 ,  H01L27/11582

    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

    Methods of forming a channel region of a transistor and methods used in forming a memory array
    45.
    发明授权
    Methods of forming a channel region of a transistor and methods used in forming a memory array 有权

    公开(公告)号：US10559466B2

    公开(公告)日：2020-02-11

    申请号：US15903280

    申请日：2018-02-23

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Anish A. Khandekar ,  Kunal Shrotri ,  Jie Li

    IPC: H01L21/02 ,  H01L27/115

    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

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