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    Semiconductor Constructions, Patterning Methods, and Methods of Forming Electrically Conductive Lines
    41.
    发明申请
    Semiconductor Constructions, Patterning Methods, and Methods of Forming Electrically Conductive Lines 有权
    形成导电线的半导体结构，图案化方法和方法

    公开(公告)号：US20140117529A1

    公开(公告)日：2014-05-01

    申请号：US13660860

    申请日：2012-10-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Vishal Sipani ,  Kyle Armstrong ,  Michael D. Hyatt ,  Michael Dean Van Patten ,  David A. Kewley ,  Ming-Chuan Yang

    IPC: H01L21/32 ,  H01L23/48 ,  H01L23/58 ,  H01L21/22 ,  H01L21/768

    CPC classification number: H01L23/525 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

    Abstract translation: 一些实施例包括形成导电线的方法。 光致抗蚀剂特征形成在衬底上，其中至少一个光致抗蚀剂特征具有变窄的区域。 修整光致抗蚀剂特征，其穿过狭窄区域以形成间隙。 隔板沿光致抗蚀剂特征的侧壁形成。 间隙中的两个垫片合并在一起。 去除光致抗蚀剂特征以留下包括间隔物的图案。 该图案延伸到衬底中以在衬底内形成多个凹槽。 导电材料形成在凹槽内以形成导电线。 一些实施例包括在半导体衬底上具有多条线的半导体结构。 两条线彼此相邻并且基本上彼此平行，除了在所述两条线彼此合并的区域中。

    Methods of Forming Memory Cells; and Methods of Forming Vertical Structures
    42.
    发明申请
    Methods of Forming Memory Cells; and Methods of Forming Vertical Structures 有权
    形成记忆细胞的方法 和垂直结构形成方法

    公开(公告)号：US20140087558A1

    公开(公告)日：2014-03-27

    申请号：US14097003

    申请日：2013-12-04

    Applicant: Micron Technology, Inc.

    Inventor： David A. Kewley ,  Brian Cleereman ,  Stephen W. Russell ,  Rex Stone ,  Anthony C. Krauth

    IPC: H01L21/3213 ,  H01L21/28

    CPC classification number: H01L21/32133 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

    Abstract translation: 一些实施例包括形成存储器的方法。 可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。 占位符可以通过间隙与所述系列的端部间隔开。 可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。 该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。 可以在第二垂直结构上形成掩模。 随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。 一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。

    Methods for forming conductive vias, and associated devices and systems
    45.
    发明授权
    Methods for forming conductive vias, and associated devices and systems 有权

    公开(公告)号：US11515204B2

    公开(公告)日：2022-11-29

    申请号：US17136287

    申请日：2020-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

    Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS
    46.
    发明申请
    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS 有权

    公开(公告)号：US20220336277A1

    公开(公告)日：2022-10-20

    申请号：US17230833

    申请日：2021-04-14

    Applicant: Micron Technology, Inc.

    Inventor： Trupti D. Gawai ,  David A. Kewley ,  Aaron M. Lowe ,  Radhakrishna Kotti ,  David S. Pratt

    IPC: H01L21/768 ,  H01L23/535

    Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS
    47.
    发明申请
    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS 有权

    公开(公告)号：US20220208606A1

    公开(公告)日：2022-06-30

    申请号：US17136287

    申请日：2020-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

    Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

    METHODS OF FORMING A STAIRCASE STRUCTURE
    48.
    发明申请
    METHODS OF FORMING A STAIRCASE STRUCTURE 有权

    公开(公告)号：US20210167079A1

    公开(公告)日：2021-06-03

    申请号：US17173405

    申请日：2021-02-11

    Applicant: Micron Technology, Inc.

    Inventor： Rohit Kothari ,  Jason C. McFarland ,  Jason Reece ,  David A. Kewley ,  Adam L. Olson

    IPC: H01L27/11556 ,  H01L21/3213 ,  H01L21/311

    Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.

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