公开(公告)号：US06803313B2

公开(公告)日：2004-10-12

申请号：US10256368

申请日：2002-09-27

申请人： Pei-Yuan Gao ,  Lu You ,  Richard J. Huang

发明人： Pei-Yuan Gao ,  Lu You ,  Richard J. Huang

IPC分类号： H01L2144

CPC分类号： H01L21/0332 ,  H01L21/32139 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.

摘要翻译： 双层BARC /硬掩模结构包括非晶碳层和形成在无定形碳层上的诸如SiON的PECVD材料的两个或更多个不同且独立形成的层。 通过独立地形成多层PECVD材料，存在于最低PECVD层中的至少一些针孔由上PECVD层封闭，因此不延伸穿过所有PECVD层。 结果，最上面的PECVD层的上表面具有比下PECVD层更低的针孔密度。 这减少了无定形碳层中的掺杂剂的光致抗蚀剂中毒，以及通过光刻胶剥离化学法蚀刻无定形碳层。

公开(公告)号：US06689684B1

公开(公告)日：2004-02-10

申请号：US09783619

申请日：2001-02-15

申请人： Lu You ,  Fei Wang ,  Richard J. Huang

发明人： Lu You ,  Fei Wang ,  Richard J. Huang

IPC分类号： H01L214763

CPC分类号： H01L21/76844 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76862 ,  H01L21/76865

摘要： Interconnects to an underlying Cu feature are formed with improved reliability by replacing a portion of the capping layer in the bottom of an opening in an overlying dielectric layer, e.g., an ILD, with a barrier material, such as Ta or TaN. During Ar sputter etching to round the ILD corners, the exposed barrier layer portion is removed and redeposited to form a liner on the side surfaces of the dielectric layer defining the opening, thereby avoiding Cu redeposition on, and/or penetration through, the side surfaces of the dielectric layer.

摘要翻译： 通过用诸如Ta或TaN的阻挡材料替换上覆电介质层（例如ILD）中的开口底部的覆盖层的一部分，形成具有改进的可靠性的互连件。 在Ar溅射蚀刻以绕过ILD拐角期间，暴露的阻挡层部分被去除并重新沉积以在限定开口的电介质层的侧表面上形成衬垫，从而避免Cu再沉积和/或穿透侧面 的介电层。

公开(公告)号：US06677679B1

公开(公告)日：2004-01-13

申请号：US09776749

申请日：2001-02-06

申请人： Lu You ,  Fei Wang ,  Dawn M. Hopper

发明人： Lu You ,  Fei Wang ,  Dawn M. Hopper

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834

摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a second etch top layer, a dielectric layer and an opening extending through the dielectric layer, the first and second etch stop layers, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The second etch stop layer is disposed over the first diffusion barrier layer, and the first etch stop layer is disposed on the second etch stop layer with a first interface therebetween. The dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer and the barrier diffusion layer can be formed from silicon nitride, and the second etch stop layer can be formed from silicon oxide. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： 半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，第二蚀刻顶层，介电层和延伸穿过介电层的开口，第一和第二蚀刻停止层以及第一蚀刻停止层 扩散阻挡层。 第一扩散阻挡层设置在第一金属化层上。 第二蚀刻停止层设置在第一扩散阻挡层上，并且第一蚀刻停止层设置在第二蚀刻停止层上，其间具有第一界面。 介电层设置在第一蚀刻停止层上。 开口也可以有圆角。 侧壁扩散阻挡层可以设置在开口的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 第一蚀刻停止层和阻挡扩散层可以由氮化硅形成，并且第二蚀刻停止层可以由氧化硅形成。 开口内的金属形成第二金属特征，金属可以包括铜或铜合金。 还公开了制造半导体器件的方法。

公开(公告)号：US06653735B1

公开(公告)日：2003-11-25

申请号：US10209447

申请日：2002-07-30

申请人： Chih Yuh Yang ,  Douglas Bonser ,  Pei-Yuan Gao ,  Lu You

发明人： Chih Yuh Yang ,  Douglas Bonser ,  Pei-Yuan Gao ,  Lu You

IPC分类号： H01L2348

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/32139

摘要： A BARC comprising materials having a lower pinhole density than that of silicon oxynitride and materials having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon is employed to reduce deformation of a pattern to be formed in a patternable layer. The patternable layer is formed over a substrate. A multi-layered anti-reflective coating is formed over the patternable layer. A photoresist pattern is formed on the coating. The coating may comprise an amorphous carbon layer formed over the patternable layer and a SiC layer having a lower pinhole density than the pinhole density of SiON formed over the amorphous carbon layer. The coating may also be formed over a polysilicon layer and comprise a thermal expansion buffer layer having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon.

摘要翻译： 使用包含具有比氮氧化硅更小的针孔密度的材料的BARC和具有比非晶碳更接近于多晶硅热膨胀系数的热膨胀系数的材料来减少将形成的图案的变形 可图案层。 可图案层形成在衬底上。 在可图案层上形成多层抗反射涂层。 在涂层上形成光致抗蚀剂图案。 涂层可以包括在可图案层上形成的无定形碳层和具有比在无定形碳层上形成的SiON的针孔密度小的针孔密度的SiC层。 涂层也可以形成在多晶硅层上，并且包括热膨胀缓冲层，其热膨胀系数比无定形碳的热膨胀系数更接近于多晶硅的热膨胀系数。

公开(公告)号：US06576545B1

公开(公告)日：2003-06-10

申请号：US09819987

申请日：2001-03-29

申请人： Dawn M. Hopper ,  Lu You ,  Minh Van Ngo

发明人： Dawn M. Hopper ,  Lu You ,  Minh Van Ngo

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/76807

摘要： Degradation of fluorine-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on a fluorine-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.

摘要翻译： 通过在层间电介质膜上形成双重性能覆盖/ ARC层，制造过程中氟掺杂二氧化硅玻璃低k层间电介质的退化显着降低，亚微米特征的分辨率得到改善。 封盖/ ARC层在氟掺杂石英玻璃层间电介质上原位形成。 封盖/ ARC层的原位形成提供了强烈粘附的封盖/ ARC层，其形成与传统封盖和ARC层相比较少的处理步骤。

公开(公告)号：US06566283B1

公开(公告)日：2003-05-20

申请号：US10073068

申请日：2002-02-12

申请人： Suzette K. Pangrle ,  Minh Van Ngo ,  Dawn Hopper ,  Lu You

发明人： Suzette K. Pangrle ,  Minh Van Ngo ,  Dawn Hopper ,  Lu You

IPC分类号： H01L2131

CPC分类号： H01L21/76831 ,  H01L21/31058 ,  H01L21/76802 ,  H01L21/76826

摘要： Improved dielectric layers are formed by surface treating the dielectric layer with a silane plasma prior to forming a subsequent layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a silane plasma produced in a PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a conductive layer within the trench.

摘要翻译： 通过在形成其之后的层之前用硅烷等离子体表面处理电介质层来形成改进的电介质层。 实施例包括在低k电介质层中形成沟槽，并通过对电介质进行在PECVD室中产生的硅烷等离子体来修饰沟槽的侧表面。 通过在包括电介质处理的侧表面的低k电介质上沉积共形阻挡层并在沟槽内沉积导电层来形成导电特征。

公开(公告)号：US06530340B2

公开(公告)日：2003-03-11

申请号：US09190721

申请日：1998-11-12

申请人： Lu You ,  Dawn Hopper ,  Richard J. Huang

发明人： Lu You ,  Dawn Hopper ,  Richard J. Huang

IPC分类号： B05C1108

CPC分类号： H01L21/76801 ,  G03F7/16 ,  H01L21/6715

摘要： This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The semiconductor thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.

摘要翻译： 本发明描述了用于半导体薄膜的旋涂沉积的改进的装置和方法。 改进的装置提供沉积室内的受控温度，压力和气体组成。 改进的方法包括通过可移动的分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液沉积在晶片上的图案。 本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。 在一个实施方案中，前体溶液从晶片的外边缘向中心分配。 在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。 本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。 本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。 通过本发明的方法生产的半导体薄膜可用于制造包括层间电介质材料的半导体器件。

公开(公告)号：US06492257B1

公开(公告)日：2002-12-10

申请号：US09498335

申请日：2000-02-04

申请人： Jeffrey A. Shields ,  Lu You ,  Mohammad R. Rakhshandehroo

发明人： Jeffrey A. Shields ,  Lu You ,  Mohammad R. Rakhshandehroo

IPC分类号： H01L214763

CPC分类号： H01L21/76802 ,  G03F7/427 ,  H01L21/31138

摘要： The degradation of deposited low dielectric constant interlayer dielectrics and gap fill layers, such as HSQ layers, during formation of contacts/vias is significantly reduced or prevented by employing a water vapor plasma to remove the photoresist mask. The use of a water vapor also enables rapid photoresist stripping at a rate of about 10 to about 20 KÅ/min. Embodiments include photoresist stripping with a water vapor plasma to prevent reduction of the number of Si—H bonds of an as-deposited HSQ layer below about 70%.

摘要翻译： 通过使用水蒸汽等离子体去除光致抗蚀剂掩模，显着降低或防止沉积的低介电常数层间电介质和间隙填充层（例如HSQ层）在形成接触/通孔期间的劣化。 使用水蒸汽还能以大约10至大约20K埃/分钟的速率快速地进行光刻胶剥离。 实施方案包括用水蒸汽等离子体进行光致抗蚀剂剥离以防止沉积的HSQ层的Si-H键的数量降低到约70％以下。

公开(公告)号：US06407009B1

公开(公告)日：2002-06-18

申请号：US09190722

申请日：1998-11-12

申请人： Lu You ,  Dawn Hopper ,  Richard J. Huang

发明人： Lu You ,  Dawn Hopper ,  Richard J. Huang

IPC分类号： H01L2130

CPC分类号： H01L21/02134 ,  B05D1/005 ,  H01L21/02282 ,  H01L21/3124

摘要： This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The semiconductor thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.

摘要翻译： 本发明描述了用于半导体薄膜的旋涂沉积的改进的装置和方法。 改进的装置提供沉积室内的受控温度，压力和气体组成。 改进的方法包括通过可移动的分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液沉积在晶片上的图案。 本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。 在一个实施方案中，前体溶液从晶片的外边缘向中心分配。 在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。 本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。 本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。 通过本发明的方法生产的半导体薄膜可用于制造包括层间电介质材料的半导体器件。

公开(公告)号：US06388309B1

公开(公告)日：2002-05-14

申请号：US09687180

申请日：2000-10-12

申请人： Lu You ,  Dawn M. Hopper ,  Richard J. Huang

发明人： Lu You ,  Dawn M. Hopper ,  Richard J. Huang

IPC分类号： H01L2358

CPC分类号： H01L21/02118 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/312 ,  H01L21/3124 ,  Y10S438/913

摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vapor deposition equipment, subject to chemical-mechanical polishing, and then processed by a conventional photolithographic process for depositing conductors. The material is then reprocessed for each successive layer of conductor separated by dielectric.

摘要翻译： 通过使用硅基低介电常数材料制造超大规模集成电路，其在化学气相沉积设备中原位旋涂，干燥，固化和封盖。 将低介电常数材料旋转，在化学气相沉积设备中进行处理，经受化学机械抛光，然后通过用于沉积导体的常规光刻工艺进行处理。 然后对由电介质隔开的导体的每个连续层重新处理该材料。