公开(公告)号：US06204136B1

公开(公告)日：2001-03-20

申请号：US09386466

申请日：1999-08-31

申请人： Simon S. Chan ,  Minh Van Ngo ,  Paul R. Besser ,  Angela T. Hui

发明人： Simon S. Chan ,  Minh Van Ngo ,  Paul R. Besser ,  Angela T. Hui

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/31116

摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.

摘要翻译： 通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣 。 实施方案包括通过进行氢离子等离子体处理来除去碳质残渣。

公开(公告)号：US06174743B1

公开(公告)日：2001-01-16

申请号：US09208623

申请日：1998-12-08

申请人： Suzette K. Pangrle ,  Paul R. Besser ,  Minh Van Ngo

发明人： Suzette K. Pangrle ,  Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L2131

CPC分类号： H01L21/3145 ,  H01L21/31612 ,  H01L21/76801

摘要： In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. During deposition, silane flow rates are regulating and reducing to less than sixty standard cubic centimeters per minute, thereby reducing the incidence of stress-induced voiding in the underlying interconnect lines. During deposition adjustments are made in deposition temperature and process pressure to control the characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing.

摘要翻译： 在基板的微电路互连线上形成层间电介质（ILD）涂层的方法中，通过使用等离子体增强化学气相沉积形成SiON层。 使用由氮气，一氧化二氮和硅烷气体形成的等离子体的沉积，其中气体以稳定的流速分配并由射频电源激励。 等离子体反应形成沉积在半导体衬底上的SiON。 在沉积期间，硅烷流速调节并降低到每分钟少于六十标准立方厘米，从而降低底层互连线中应力引起的空隙的发生。 在淀积温度和工艺压力下进行沉积调整，以控制SiON层的特性。 测试SiON层的可接受的光学性能，并且用SiO 2层涂覆可接受的SiON层以完成ILD的形成。 一旦形成了ILD，底物就可以进行进一步的处理。

公开(公告)号：US6150285A

公开(公告)日：2000-11-21

申请号：US99057

申请日：1998-06-17

申请人： Paul R. Besser ,  Minh Van Ngo

发明人： Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76801

摘要： A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposition, excess TEOS is etched away, thereby avoiding hydrogen embrittlement of and subsequent void formation in the aluminum lines that could otherwise occur if silane were used as the HDP ILD.

摘要翻译： 制造0.25微米半导体芯片的方法包括使用TEOS作为高密度等离子体（HDP）层间电介质（ILD）。 更具体地说，在基板上建立预定的铝线图案之后，TEOS沉积并与TEOS沉积同时被蚀刻掉，从而避免了铝线中的氢脆化和随后的空隙形成，否则如果硅烷是 用作HDP ILD。

公开(公告)号：US07407882B1

公开(公告)日：2008-08-05

申请号：US10928665

申请日：2004-08-27

申请人： Connie Pin-Chin Wang ,  Paul R. Besser ,  Wen Yu ,  Jinsong Yin ,  Keizaburo Yoshie

发明人： Connie Pin-Chin Wang ,  Paul R. Besser ,  Wen Yu ,  Jinsong Yin ,  Keizaburo Yoshie

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76856

摘要： A semiconductor component having a titanium silicide contact structure and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate. An opening having sidewalls is formed in the dielectric layer and exposes a portion of the semiconductor substrate. Titanium silicide is disposed on the dielectric layer, sidewalls, and the exposed portion of the semiconductor substrate. The titanium silicide may be formed by disposing titanium on the dielectric layer, sidewalls, and exposed portion of the semiconductor substrate and reacting the titanium with silane. Alternatively, the titanium silicide may be sputter deposited. A layer of titanium nitride is formed on the titanium silicide. A layer of tungsten is formed on the titanium nitride. The tungsten, titanium nitride, and titanium silicide are polished to form the contact structures.

摘要翻译： 具有硅化钛接触结构的半导体部件和半导体部件的制造方法。 在半导体衬底上形成介电材料层。 在电介质层中形成具有侧壁的开口，并露出半导体衬底的一部分。 钛硅化物设置在电介质层，侧壁和半导体衬底的暴露部分上。 钛硅化物可以通过在电介质层，侧壁和半导体衬底的暴露部分上设置钛并使钛与硅烷反应而形成。 或者，可以溅射沉积钛硅化物。 在硅化钛上形成氮化钛层。 在氮化钛上形成钨层。 将钨，氮化钛和硅化钛抛光以形成接触结构。

公开(公告)号：US08728931B2

公开(公告)日：2014-05-20

申请号：US13553977

申请日：2012-07-20

申请人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

发明人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC分类号： H01L21/4763

CPC分类号： H01L23/49866 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

摘要翻译： 形成互连结构的方法包括在基板的电介质层中形成凹部。 形成粘合阻挡层以使凹部成线。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 该凹部填充有填充层。

公开(公告)号：US20130049199A1

公开(公告)日：2013-02-28

申请号：US13222469

申请日：2011-08-31

申请人： Paul R. Besser ,  Roy A. Carruthers ,  Christopher P. D'Emic ,  Christian Lavoie ,  Conal E. Murray ,  Kazuya Ohuchi ,  Christopher Scerbo ,  Bin Yang

发明人： Paul R. Besser ,  Roy A. Carruthers ,  Christopher P. D'Emic ,  Christian Lavoie ,  Conal E. Murray ,  Kazuya Ohuchi ,  Christopher Scerbo ,  Bin Yang

IPC分类号： H01L23/532 ,  H01L21/336 ,  H01L21/768

CPC分类号： H01L21/26506 ,  H01L21/28518 ,  H01L29/00 ,  H01L29/665 ,  H01L29/7833

摘要： Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to form an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A suicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.

摘要翻译： 具有改进的稀土硅化物形态的硅化技术用于制造半导体器件触点。 例如，用于形成硅化物的方法包括用非晶化物质注入硅层以在硅层中形成非晶硅区域，并在与非晶硅区域接触的硅层上沉积稀土金属膜。 然后进行自杀处理以组合稀土金属膜和非晶硅区域，以在硅层上形成硅化物膜。

公开(公告)号：US07994038B2

公开(公告)日：2011-08-09

申请号：US12366378

申请日：2009-02-05

申请人： Karthik Ramani ,  Paul R. Besser

发明人： Karthik Ramani ,  Paul R. Besser

IPC分类号： H01L21/3205

CPC分类号： H01L21/823807 ,  H01L21/28052 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/458 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

摘要： Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.

摘要翻译： 晶体管器件形成有硅化镍层，配制成防止去除上覆应力衬垫时的退化。 实施方案包括具有镍化硅层的晶体管，其铂组分梯度朝向其上表面增加铂含量，即铂在远离栅电极和源/漏区的方向上增加。 实施例包括形成具有第一量的铂的第一镍层，并在第一层镍上形成具有第二量铂的第二层镍，第二重量百分比的铂大于第一重量百分数。 然后将镍层退火以形成铂化合物梯度朝向上表面逐渐增加的铂硅化镍层。 铂浓度梯度在后续处理期间保护硅化镍层，如在蚀刻期间去除上覆的应力衬垫，从而避免器件性能的降低。

公开(公告)号：US07910996B2

公开(公告)日：2011-03-22

申请号：US12496133

申请日：2009-07-01

申请人： Paul R. Besser ,  Scott D. Luning

发明人： Paul R. Besser ,  Scott D. Luning

IPC分类号： H01L29/12

CPC分类号： H01L29/66628 ,  H01L29/66772

摘要： A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

摘要翻译： 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

公开(公告)号：US20080182407A1

公开(公告)日：2008-07-31

申请号：US11669700

申请日：2007-01-31

申请人： Jun Zhai ,  Christy Woo ,  Kok-Yong Yiang ,  Paul R. Besser ,  Richard C. Blish ,  Christine Hau-Reige

发明人： Jun Zhai ,  Christy Woo ,  Kok-Yong Yiang ,  Paul R. Besser ,  Richard C. Blish ,  Christine Hau-Reige

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76852 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A via is formed in contact with a conductive line, whereby the via is offset from the conductive line so that the via extends beyond the conductive line. In accordance with a specific embodiment, a portion of the via contacts a sidewall of the conductive line.

摘要翻译： 通孔形成为与导电线接触，由此通孔偏离导线，使得通孔延伸超过导线。 根据具体实施例，通孔的一部分接触导线的侧壁。

公开(公告)号：US20080150011A1

公开(公告)日：2008-06-26

申请号：US11958646

申请日：2007-12-18

申请人： Simon Siu-Sing Chan ,  Lei Xue ,  YouSeok Suh ,  Amol Ramesh Joshi ,  Hidehiko Shiraiwa ,  Harpreet Sachar ,  Kuo-Tung Chang ,  Connie Pin Chin Wang ,  Paul R. Besser ,  Shenqing Fang ,  Meng Ding ,  Takashi Orimoto ,  Wei Zheng ,  Fred TK Cheung

发明人： Simon Siu-Sing Chan ,  Lei Xue ,  YouSeok Suh ,  Amol Ramesh Joshi ,  Hidehiko Shiraiwa ,  Harpreet Sachar ,  Kuo-Tung Chang ,  Connie Pin Chin Wang ,  Paul R. Besser ,  Shenqing Fang ,  Meng Ding ,  Takashi Orimoto ,  Wei Zheng ,  Fred TK Cheung

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.

摘要翻译： 提供一种用于形成集成电路系统的方法，包括形成具有芯区域和周边区域的衬底，在芯区域中的衬底上形成电荷存储堆叠，形成具有堆叠集管的栅极堆叠，堆叠集束具有金属部分 衬底，并且在电荷存储堆叠上形成具有堆叠头的存储器系统。