公开(公告)号：US06171919B2

公开(公告)日：2001-01-09

申请号：US09361155

申请日：1999-07-27

申请人： Paul R. Besser ,  Minh Van Ngo ,  Simon S. Chan ,  Angela T. Hui

发明人： Paul R. Besser ,  Minh Van Ngo ,  Simon S. Chan ,  Angela T. Hui

IPC分类号： H01L21336

CPC分类号： H01L29/665

摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.

摘要翻译： 通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣 。 实施例包括通过进行氢离子等离子体处理来除去碳质残渣。

公开(公告)号：US06204136B1

公开(公告)日：2001-03-20

申请号：US09386466

申请日：1999-08-31

申请人： Simon S. Chan ,  Minh Van Ngo ,  Paul R. Besser ,  Angela T. Hui

发明人： Simon S. Chan ,  Minh Van Ngo ,  Paul R. Besser ,  Angela T. Hui

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/31116

摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.

摘要翻译： 通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣 。 实施方案包括通过进行氢离子等离子体处理来除去碳质残渣。

公开(公告)号：US6143672A

公开(公告)日：2000-11-07

申请号：US084442

申请日：1998-05-22

申请人： Minh Van Ngo ,  Simon S. Chan ,  Suzette K. Pangrle ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Simon S. Chan ,  Suzette K. Pangrle ,  Robert A. Huertas

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/76 ,  H01L21/469

CPC分类号： H01L21/02164 ,  C23C16/402 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/76801

摘要： In one embodiment, the present invention relates to a method of depositing a dielectric layer over a stacked interconnect structure, involving the steps of: providing a substrate having at least one stacked interconnect structure comprising at least one of an aluminum layer and an aluminum alloy layer; depositing the dielectric layer over the stacked interconnect structureunder a pressure from about 1 mTorr to about 6 mTorr, an O.sub.2 flow rate from about 110 sccm to about 130 sccm and a silane flow rate from about 52 sccm to about 60 sccm at a bias power from about 2500 W to about 3100 W,under a pressure from about 2 Torr to about 2.8 Torr, an N.sub.2 flow rate from about 7 l to about 11.5 l, an N.sub.2 O flow rate from about 1 l to about 2 l and a silane flow rate from about 250 sccm to about 300 sccm at a power from about 900 W to about 1300 W at a temperature from about 300.degree. C. to about 350.degree. C., orunder a pressure from about 2 Torr to about 2.8 Torr, an N.sub.2 flow rate from about 7 l to about 11.5 l, an N.sub.2 O flow rate from about 1 l to about 2 l and a silane flow rate from about 80 sccm to about 120 sccm at a power from about 900 W to about 1300 W at a temperature from about 390.degree. C. to about 410.degree. C.

摘要翻译： 在一个实施例中，本发明涉及一种在堆叠的互连结构上沉积电介质层的方法，其包括以下步骤：提供具有至少一个堆叠互连结构的衬底，所述堆叠互连结构包括铝层和铝合金层中的至少一个 ; 在约1mTorr至约6mTorr的压力下，将电介质层沉积在堆叠的互连结构上，O 2流速为约110sccm至约130sccm，硅烷流速为约52sccm至约60sccm，偏置功率 约2500W至约3100W，在约2托至约2.8托的压力下，N 2流速为约7升至约11.5升，N 2 O流速为约1升至约2升，硅烷流量 在约300至约350℃的温度或约2托至约2.8托的压力下以约900至约1300瓦的功率从约250sccm至约300sccm的速率， N 2流速为约7升至约11.5升，N 2 O流速为约1升至约2升，硅烷流速为约80sccm至约120sccm，功率为约900W至约1300W， 温度约390℃至约410℃

公开(公告)号：US06251776B1

公开(公告)日：2001-06-26

申请号：US09283754

申请日：1999-04-02

申请人： Minh Van Ngo ,  Simon S. Chan ,  Anne E. Sanderfer ,  King Wai Kelwin Ko

发明人： Minh Van Ngo ,  Simon S. Chan ,  Anne E. Sanderfer ,  King Wai Kelwin Ko

IPC分类号： H01L21441

CPC分类号： H01L21/02071 ,  H01L21/02052 ,  H01L21/02054 ,  H01L21/76838

摘要： Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a plasma containing ammonia or ammonia and oxygen at a temperature of at least about 400° C. and gap filling with a dielectric material, e.g. HDP oxide by HDP CVD.

摘要翻译： 通过在间隙填充之前去除蚀刻残留物来避免或显着减少图形化金属层的应力腐蚀引起的空隙。 实施例包括使用氟和/或氯化学，湿洗，用至少约400℃的温度下含有氨或氨和等离子体的等离子体进行蚀刻Al或Al合金层，以及填充介电材料的间隙。 HDP CVD的HDP氧化物。

公开(公告)号：US20090050471A1

公开(公告)日：2009-02-26

申请号：US11844518

申请日：2007-08-24

申请人： Robert J. Chiu ,  Connie Pin-Chin Wang ,  Minh Van Ngo ,  Simon S. Chan

发明人： Robert J. Chiu ,  Connie Pin-Chin Wang ,  Minh Van Ngo ,  Simon S. Chan

IPC分类号： C23C14/32

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76814 ,  H01L23/485

摘要： A process of forming an electronic device can include depositing a first layer over a substrate and depositing a second layer over the first layer. In one embodiment, depositing the first layer is performed at a first alternating current (“AC”) power, and depositing the second layer is performed at a second AC power that is different from the first AC power. In another embodiment, the first layer is formed by a physical vapor deposition technique at a first power sufficient to remove the insulating layer using first metal ions, wherein the first layer includes an overhanging portion extending over the bottom of the opening. In a further embodiment, the second layer is formed by the physical vapor deposition technique using second metal ions and a second power sufficient to reduce a lateral dimension of the overhanging portion.

摘要翻译： 形成电子器件的过程可以包括在衬底上沉积第一层并在第一层上沉积第二层。 在一个实施例中，在第一交流（“AC”）功率下执行沉积第一层，并且以不同于第一AC电力的第二AC电源执行沉积第二层。 在另一个实施例中，第一层通过物理气相沉积技术以足以使用第一金属离子去除绝缘层的第一功率形成，其中第一层包括在开口底部延伸的伸出部分。 在另一个实施例中，第二层通过使用第二金属离子的物理气相沉积技术和足以减少突出部分的横向尺寸的第二功率形成。

公开(公告)号：US06333263B1

公开(公告)日：2001-12-25

申请号：US09285388

申请日：1999-04-02

申请人： Minh Van Ngo ,  Simon S. Chan ,  Anne E. Sanderfer ,  King Wai Kelwin Ko

发明人： Minh Van Ngo ,  Simon S. Chan ,  Anne E. Sanderfer ,  King Wai Kelwin Ko

IPC分类号： H01L2144

CPC分类号： H01L21/76838

摘要： Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a nitrogen-containing plasma at a temperature of at least about 400° C. and gap filling with a dielectric material, e.g. HDP oxide by HDPCVD.

摘要翻译： 通过在间隙填充之前去除蚀刻残留物来避免或显着减少图形化金属层的应力腐蚀引起的空隙。 实施方案包括使用氟和/或氯化学，湿法清洗，在至少约400℃的温度下用含氮等离子体进行蚀刻和用电介质材料填充间隙来蚀刻Al或Al合金层。 HDPVD的HDP氧化物。

公开(公告)号：US08652907B2

公开(公告)日：2014-02-18

申请号：US13071385

申请日：2011-03-24

申请人： Chuan Lin ,  Hidehiko Shiraiwa ,  Bradley Marc Davis ,  Lei Xue ,  Simon S. Chan ,  Kenichi Ohtsuka ,  Angela T. Hui ,  Scott Allan Bell

发明人： Chuan Lin ,  Hidehiko Shiraiwa ,  Bradley Marc Davis ,  Lei Xue ,  Simon S. Chan ,  Kenichi Ohtsuka ,  Angela T. Hui ,  Scott Allan Bell

IPC分类号： H01L21/28 ,  H01L21/8234

CPC分类号： H01L29/4916 ,  H01L21/28044 ,  H01L21/823456 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/78

摘要： A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.

摘要翻译： 提供一种制造集成电路的方法，该集成电路包括具有不同多晶硅栅极结构的第一区域和第二区域。 该方法包括在第一和第二区域上沉积第一多晶硅层，并在第二区域内在第一多晶硅层上沉积氧化物层。 在第一多晶硅层和氧化物区域上沉积第二多晶硅层。 然后剥离位于氧化物区域上方的第二多晶硅层的一部分。

公开(公告)号：US20120241871A1

公开(公告)日：2012-09-27

申请号：US13071385

申请日：2011-03-24

申请人： Chuan Lin ,  Hidehiko Shiraiwa ,  Bradley Marc Davis ,  Lei Xue ,  Simon S. Chan ,  Kenichi Ohtsuka ,  Angela T. Hui ,  Scott Allan Bell

发明人： Chuan Lin ,  Hidehiko Shiraiwa ,  Bradley Marc Davis ,  Lei Xue ,  Simon S. Chan ,  Kenichi Ohtsuka ,  Angela T. Hui ,  Scott Allan Bell

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/4916 ,  H01L21/28044 ,  H01L21/823456 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/78

摘要： A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.

摘要翻译： 提供一种制造集成电路的方法，该集成电路包括具有不同多晶硅栅极结构的第一区域和第二区域。 该方法包括在第一和第二区域上沉积第一多晶硅层，并在第二区域内在第一多晶硅层上沉积氧化物层。 在第一多晶硅层和氧化物区域上沉积第二多晶硅层。 然后剥离位于氧化物区域上方的第二多晶硅层的一部分。

公开(公告)号：US08314454B2

公开(公告)日：2012-11-20

申请号：US12970687

申请日：2010-12-16

申请人： Simon S. Chan

发明人： Simon S. Chan

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

公开(公告)号：US07144818B2

公开(公告)日：2006-12-05

申请号：US10729479

申请日：2003-12-05

申请人： Mario M. Pelella ,  Simon S. Chan

发明人： Mario M. Pelella ,  Simon S. Chan

IPC分类号： H01L21/311

CPC分类号： H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3043 ,  H01L29/7842

摘要： A method of manufacturing an integrated circuit (IC) can utilizes semiconductor substrate configured in accordance with a trench process. The substrate utilizes trenches in a base layer to induce stress in a layer. The substrate can include silicon. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.

摘要翻译： 集成电路（IC）的制造方法可以利用根据沟槽工艺配置的半导体衬底。 衬底利用基层中的沟槽以在层中引起应力。 衬底可以包括硅。 沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。