公开(公告)号：US4988635A

公开(公告)日：1991-01-29

申请号：US356144

申请日：1989-05-24

申请人： Natsuo Ajika ,  Hideaki Arima

发明人： Natsuo Ajika ,  Hideaki Arima

IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A memory cell of 1 bit is constituted by 1 selecting transistor and 1 memory transistor in an EEPROM. One of the source-drain regions is commonly used by the selecting transistor and the memory transistor. The commonly used source-drain region is manufactured through the following steps. First, a gate electrode of the transistor is formed. An oxide film is deposited on the entire surface. A resist is applied thereon and is etched back to expose a surface of the oxide film on the gate electrode. Thereafter, the oxide films deposited on the side surfaces of the gate electrode are removed to form opening portions. Impurities are implanted to the silicon substrate utilizing the opening portions.

摘要翻译： 1位的存储单元由EEPROM中的1个选择晶体管和1个存储晶体管构成。 源极 - 漏极区之一通常由选择晶体管和存储晶体管使用。 常用的源极 - 漏极区域通过以下步骤制造。 首先，形成晶体管的栅电极。 氧化膜沉积在整个表面上。 将抗蚀剂施加在其上并被回蚀以暴露栅电极上的氧化膜的表面。 此后，去除沉积在栅电极的侧表面上的氧化膜以形成开口部分。 利用开口部分将杂质植入硅衬底。

公开(公告)号：US20100149875A1

公开(公告)日：2010-06-17

申请号：US12714750

申请日：2010-03-01

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及非易失性半导体存储器，更具体地说涉及具有增加的程序吞吐量的非易失性半导体存储器 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US20090090961A1

公开(公告)日：2009-04-09

申请号：US12246193

申请日：2008-10-06

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  G11C16/0441 ,  G11C16/0491 ,  H01L21/26586 ,  H01L29/792

摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

摘要翻译： 非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部 所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层， 形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散 肋骨中的结构是不对称的。

公开(公告)号：US20080186766A1

公开(公告)日：2008-08-07

申请号：US12025566

申请日：2008-02-04

申请人： Taku Ogura ,  Natsuo Ajika

发明人： Taku Ogura ,  Natsuo Ajika

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit lines, each of the sub-bit lines being connected to drains of the P type non-volatile memory cells in a respective one of columns of the matrix; a first P type well; and a plurality of N type selection transistors, each of the selection transistors selectively connecting a respective one of sub-bit lines to a corresponding one of main bit lines.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括：第一N型阱; 多个P型非易失性存储单元，被布置成矩阵形成在N型阱中; 多个子位线，每个子位线连接到矩阵的相应列中的P型非易失性存储单元的漏极; 第一个P型井; 和多个N型选择晶体管，所述选择晶体管中的每一个选择性地将相应的一个子位线连接到相应的一个主位线。

公开(公告)号：US5798289A

公开(公告)日：1998-08-25

申请号：US716851

申请日：1996-09-10

申请人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

发明人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817 ,  H01L27/10852

摘要： A method of manufacturing a semiconductor memory device having stacked capacitors is disclosed. After forming a capacitor isolating layer on an insulation layer and forming a contact hole in the insulation layer, a first conductive layer is formed on the insulating layer and the capacitor isolating layer and on an inner surface of the contact hole. The first conductive layer is partially etched and removed by using an etch-back technique to be isolated into a first capacitor portion and a second capacitor portion. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.

摘要翻译： 公开了一种制造具有层叠电容器的半导体存储器件的方法。 在绝缘层上形成电容器隔离层并在绝缘层中形成接触孔之后，在绝缘层和电容器隔离层上以及接触孔的内表面上形成第一导电层。 通过使用蚀刻技术将第一导电层部分地蚀刻和去除，以将其隔离成第一电容器部分和第二电容器部分。 在第一导电层上形成电介质层。 在介电层上形成第二导电层。

公开(公告)号：US5621689A

公开(公告)日：1997-04-15

申请号：US457708

申请日：1995-06-01

申请人： Kiyohiko Sakakibara ,  Natsuo Ajika

发明人： Kiyohiko Sakakibara ,  Natsuo Ajika

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/14 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115

摘要： It is postulated that a nonvolatile semiconductor memory device of the present invention includes a charge pump. The nonvolatile semiconductor memory device includes a memory cell array unit having a plurality of memory transistors formed therein to store data. Each memory transistor has a drain region connected to a predetermined bit line BL which is connected to a write circuit. A charge pump is connected to the write circuit. A predetermined potential is applied to a memory transistor via the write circuit by this charge pump in a writing mode. A charge pump load control means for suppressing variation in the charge pump load is connected to a memory transistor or a well region in which the memory transistor is formed. Thus, the charge pump load can be stabilized to allow improvement of the writing or erasing characteristics of the nonvolatile semiconductor memory device.

摘要翻译： 假设本发明的非易失性半导体存储器件包括电荷泵。 非易失性半导体存储器件包括具有形成在其中以存储数据的多个存储晶体管的存储单元阵列单元。 每个存储晶体管具有连接到写入电路的预定位线BL的漏极区域。 电荷泵连接到写入电路。 通过该电荷泵以写入模式将预定电位经由写入电路施加到存储晶体管。 用于抑制电荷泵负载变化的电荷泵负载控制装置连接到其中形成存储晶体管的存储晶体管或阱区。 因此，可以稳定电荷泵负载，以提高非易失性半导体存储器件的写入或擦除特性。

公开(公告)号：US5523596A

公开(公告)日：1996-06-04

申请号：US403614

申请日：1995-03-14

申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika

发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L27/04 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  Y10S438/954

摘要： A capacitor includes a polycrystalline silicon layer 1 as a lower electrode layer, a dielectric layer 112, and a polycrystalline silicon layer 113 as an upper electrode layer. The dielectric layer 112 is formed by an oxynitride film 2, a silicon nitride film 3 and a top oxide film 4. A film thickness t.sub.3 of the top oxide film 4 is controlled to be less than 20 .ANG.. Capacitance of the capacitor can be increased while improving the duration of life of the dielectric layer, resulting in a highly reliable capacitor.

摘要翻译： 电容器包括作为下电极层的多晶硅层1，电介质层112和作为上电极层的多晶硅层113。 电介质层112由氧氮化物膜2，氮化硅膜3和顶部氧化物膜4形成。顶部氧化膜4的膜厚度t3被控制为小于20安培。 可以增加电容器的电容，同时改善电介质层的寿命，导致高度可靠的电容器。

公开(公告)号：US5428235A

公开(公告)日：1995-06-27

申请号：US300878

申请日：1994-09-06

申请人： Masahiro Shimizu ,  Takehisa Yamaguchi ,  Natsuo Ajika

发明人： Masahiro Shimizu ,  Takehisa Yamaguchi ,  Natsuo Ajika

IPC分类号： H01L27/108 ,  H01L29/68

CPC分类号： H01L27/10808

摘要： A memory cell of a DRAM comprises one MOS transistor and one capacitor. The MOS transistor includes a pair of source/drain regions and a gate electrode formed on the channel region. A bit line is formed so as to be connected to the source/drain region. A conductive layer is formed so as to be connected to the source/drain region. The gate electrode includes a first part formed on the channel region with an oxide film interposedand second and third parts extending from the first part, respectively, and formed on the bit line and the conductive layer with an interlayer oxide film interposed. The capacitor includes a lower electrode formed so as to be connected to the conductive layer and an upper electrode formed so as to be opposed to the surface of the lower electrode with a dielectric film interposed. The upper electrode is placed above the bit line. A word line is placed above the upper electrode and connected to the gate electrode. It is possible to provide a field effect transistor in which increase in speed can be realized and to provide a semiconductor memory device in which capacitance of the capacitor can be sufficiently secured in case of making miniaturization of the memory cell. It is also possible to prevent decrease in reliability caused by disconnection of the bit line.

摘要翻译： DRAM的存储单元包括一个MOS晶体管和一个电容器。 MOS晶体管包括一对源极/漏极区域和形成在沟道区域上的栅极电极。 形成位线以便连接到源极/漏极区域。 导电层形成为连接到源/漏区。 栅电极包括形成在沟道区上的第一部分，其中介于氧化膜之间，第二和第三部分分别从第一部分延伸并且形成在位线上，并且导电层被插入夹层氧化膜。 电容器包括形成为连接到导电层的下电极和形成为与介电膜插入的下电极的表面相对的上电极。 上电极位于位线上方。 字线放置在上电极上方并连接到栅电极。 可以提供一种可以实现速度增加的场效应晶体管，并且提供一种在使存储单元小型化的情况下能够充分确保电容器的电容的半导体存储器件。 也可以防止由位线的断线引起的可靠性降低。

公开(公告)号：US5355012A

公开(公告)日：1994-10-11

申请号：US52858

申请日：1993-04-28

申请人： Yasuo Yamaguchi ,  Natsuo Ajika ,  Tsuyoshi Yamano

发明人： Yasuo Yamaguchi ,  Natsuo Ajika ,  Tsuyoshi Yamano

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L33/00

CPC分类号： H01L29/78612

摘要： A semiconductor device is an SOI type field effect transistor in which an active region is isolated and insulated by a transistor for isolation. A contact hole for isolation is formed in a gate dielectric thin film for isolation between a gate electrode of the transistor for isolation and a channel region below the gate electrode. In the semiconductor device thus structured, surplus carriers produced in a channel region below a transfer gate electrode are drawn through channel region and isolation contact hole into isolation gate electrode, thereby preventing such a disadvantageous phenomenon as a kink effect or the like due to a floating-substrate effect.

摘要翻译： 半导体器件是SOI型场效应晶体管，其中有源区被隔离的晶体管隔离并绝缘。 用于隔离的接触孔形成在用于隔离的晶体管的栅电极和栅电极下方的沟道区之间隔离的栅极电介质薄膜中。 在这样构成的半导体装置中，在传输栅电极下方的沟道区域产生的多余载流子通过沟道区域和隔离接触孔被吸入隔离栅电极，从而防止由于浮动而引起的扭结效应等不利现象 - 底物效应。

公开(公告)号：US5233212A

公开(公告)日：1993-08-03

申请号：US692395

申请日：1991-04-25

申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L21/76801 ,  H01L21/76834 ,  H01L27/10808 ,  Y10S257/90

摘要： A semiconductor device includes a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) re smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resin film in patterning the conductive interconnection layer.

摘要翻译： 半导体器件包括布置在半导体衬底（1）的表面上的多个栅电极（6a，6b，6c，6d），绝缘层（5,8）覆盖了栅电极的顶部和侧壁。 在元件隔离区域（2）的表面上的相邻栅电极的相对侧壁之间的间隔小于栅电极侧壁的绝缘层中最薄绝缘层（8）的厚度的两倍 活性区的表面。 元件隔离区域上的栅电极之间的空间（14）填充有绝缘隔离层（8），使得要形成导电互连层（10）的元件隔离区域上的下面部分的不均匀性减小 防止导电互连层变薄，并且在图案化导电互连层时由于树脂膜的过度蚀刻而导致的断开。