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    P-type nitride semiconductor structure and bipolar transistor
    41.
    发明申请
    P-type nitride semiconductor structure and bipolar transistor 有权
    P型氮化物半导体结构和双极晶体管

    公开(公告)号：US20050224831A1

    公开(公告)日：2005-10-13

    申请号：US10516380

    申请日：2004-01-06

    申请人： Toshiki Makimoto ,  Kazuhide Kumakura ,  Naoki Kobayashi

    发明人： Toshiki Makimoto ,  Kazuhide Kumakura ,  Naoki Kobayashi

    IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L29/20 ,  H01L29/737 ,  H01L33/00

    CPC分类号： H01L29/66318 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/7371

    摘要： A nitride semiconductor structure is provided which greatly improves ohmic characteristics by repairing process damage by regrowing an indium-containing p-type nitride semiconductor on a p-type nitride semiconductor having the process damage. In addition, a nitride semiconductor bipolar transistor is provided which can greatly improve its current gain and offset voltage. The structure includes an indium-containing p-type nitride semiconductor layer on a p-type nitride semiconductor processed by etching. The bipolar transistor, which has a base layer composed of a p-type nitride semiconductor, has an indium-containing p-type InGaN base layer regrown on a surface of a p-type InGaN base layer exposed by etching an emitter layer.

    摘要翻译： 提供了一种氮化物半导体结构，其通过在具有工艺损伤的p型氮化物半导体上重新生长含铟p型氮化物半导体来修复工艺损伤而极大地改善欧姆特性。 此外，提供可以大大提高其电流增益和偏移电压的氮化物半导体双极晶体管。 该结构包括通过蚀刻处理的p型氮化物半导体上的含铟p型氮化物半导体层。 具有由p型氮化物半导体构成的基极层的双极晶体管在通过蚀刻发射极层而露出的p型InGaN基底层的表面上再生长含有铟的p型InGaN基极层。

    Organic EL display apparatus
    42.
    发明申请
    Organic EL display apparatus 失效
    有机EL显示装置

    公开(公告)号：US20050219167A1

    公开(公告)日：2005-10-06

    申请号：US11092606

    申请日：2005-03-30

    申请人： Reiji Hattori ,  Hisao Tanabe ,  Naoki Kobayashi ,  Yasushi Sato

    发明人： Reiji Hattori ,  Hisao Tanabe ,  Naoki Kobayashi ,  Yasushi Sato

    IPC分类号： H01L51/50 ,  G09F9/30 ,  G09G3/20 ,  G09G3/30 ,  H01L27/32 ,  H05B33/14

    CPC分类号： G09G3/3233 ,  G09G3/3291 ,  G09G2300/0465 ,  G09G2300/0819 ,  G09G2300/0833 ,  G09G2300/0842 ,  G09G2360/147

    摘要： Disclosed is an organic EL display apparatus comprising: a light emitting section; a current control section which controls a current to be flown to the light emitting section; a photoelectric converting section which generates a current upon detecting light emitted from the light emitting section; a first switching section which switches between transmission and non-transmission of the current generated; an amplifying section which performs current-voltage conversion of the current transmitted by the first switching section and amplifies it; a comparison amplifying section which performs comparison and amplification of a voltage value obtained by the amplification and a voltage value corresponding to the image signal; a second switching section which switches between transmission and non-transmission of the voltage value resulting from the comparison and amplification; and an image signal holding capacitor which is charged or discharged according to the voltage value transmitted by the second switching section.

    摘要翻译： 公开了一种有机EL显示装置，包括：发光部; 电流控制部，其控制流向所述发光部的电流; 光电转换部，其在检测从所述发光部发出的光时产生电流; 第一切换部，其在所产生的电流的传输和不传输之间切换; 放大部，其对由所述第一开关部发送的电流进行电流电压转换，并对其进行放大; 比较放大部，其对通过放大获得的电压值和对应于图像信号的电压值进行比较和放大; 第二切换部，其在由比较和放大产生的电压值的传输和非传输之间切换; 以及根据由第二切换部发送的电压值进行充放电的图像信号保持电容器。

    Nonvolatile semiconductor memory device
    43.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US06903975B2

    公开(公告)日：2005-06-07

    申请号：US10786025

    申请日：2004-02-26

    申请人： Shunichi Saeki ,  Hideakii Kurata ,  Naoki Kobayashi

    发明人： Shunichi Saeki ,  Hideakii Kurata ,  Naoki Kobayashi

    IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/28 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00

    CPC分类号： G11C16/3459 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/3454 ,  G11C2211/5621

    摘要： A nonvolatile semiconductor memory device includes a memory cell, formed in a well in a substrate and having a source, a drain, a first gate and a second gate. A word line control circuit drives a word line connected to the second gate, a program data holding circuit holds program data, a programming voltage generator circuit applies a programming voltage onto a bit line connected to the drain, and a discrimination circuit verifies the program data. Programming is conducted by applying positive voltages to the second gate and drain, while injecting hot electrons generated in a channel portion in a vicinity of the drain when 0V is applied to the well and source to increase a threshold voltage. Verification is conducted by applying a verify voltage to the second gate, while applying a positive voltage to the drain and 0V to the well and source, thereby verifying whether the positive voltage applied is maintained or comes down to 0V, depending upon the threshold voltage, by means of the discrimination circuit.

    摘要翻译： 非易失性半导体存储器件包括形成在衬底中的阱中并具有源极，漏极，第一栅极和第二栅极的存储单元。 字线控制电路驱动连接到第二门的字线，程序数据保持电路保存程序数据，编程电压发生器电路将编程电压施加到与漏极连接的位线上，鉴别电路验证程序数据 。 通过向第二栅极和漏极施加正电压，同时在向阱和源施加0V以增加阈值电压时注入在漏极附近的通道部分中产生的热电子来进行编程。 通过向第二栅极施加验证电压，同时向漏极施加正电压，向阱和源施加0V，从而根据阈值电压验证施加的正电压是否维持或降至0V， 通过鉴别电路。

    Data processing apparatus and data processing method
    46.
    发明授权
    Data processing apparatus and data processing method 失效

    公开(公告)号：US06728310B1

    公开(公告)日：2004-04-27

    申请号：US09434788

    申请日：1999-11-05

    申请人： Tetsujiro Kondo ,  Naoki Kobayashi ,  Koji Ohta

    发明人： Tetsujiro Kondo ,  Naoki Kobayashi ,  Koji Ohta

    IPC分类号： H04B1700

    CPC分类号： H03H21/0012 ,  H04N5/21

    摘要： A data processing apparatus processes input data and outputs the processed data. The data processing apparatus includes a data processing section for processing the input data by a predetermined processing method and outputting the processed data, an input-data evaluation section for evaluating the input data, an output-data evaluation section for evaluating the output data, and a real-time learning section for controlling such that the processing method is learned in real time according to the evaluation results obtained by the input-data evaluation section and the output-data evaluation section and the data processing section processes the input data according to the learned processing method, and thereby, improves the output data every moment.

    Programming method of nonvolatile semiconductor memory device
    47.
    发明授权
    Programming method of nonvolatile semiconductor memory device 有权

    公开(公告)号：US06636437B2

    公开(公告)日：2003-10-21

    申请号：US10260407

    申请日：2002-10-01

    申请人： Naoki Kobayashi ,  Hideaki Kurata ,  Katsutaka Kimura ,  Takashi Kobayashi ,  Shunichi Saeki

    发明人： Naoki Kobayashi ,  Hideaki Kurata ,  Katsutaka Kimura ,  Takashi Kobayashi ,  Shunichi Saeki

    IPC分类号： G11C1604

    CPC分类号： G11C11/5628

    摘要： In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed within groups of threshold voltages, starting from the nearer threshold voltage to the erased state within each group. When writing each of the data having the other threshold voltages, writing of the data is performed to a memory cell beginning with those groups having the remoter threshold voltages from the erased state.

    Data converting apparatus, method thereof, and recording medium
    48.
    发明授权
    Data converting apparatus, method thereof, and recording medium 失效
    数据转换装置，方法和记录介质

    公开(公告)号：US06385249B1

    公开(公告)日：2002-05-07

    申请号：US09572260

    申请日：2000-05-17

    申请人： Tetsujiro Kondo ,  Kenji Takahashi ,  Naoki Kobayashi ,  Yoshinori Watanabe

    发明人： Tetsujiro Kondo ,  Kenji Takahashi ,  Naoki Kobayashi ,  Yoshinori Watanabe

    IPC分类号： H04N712

    CPC分类号： G06T3/40 ,  H04N19/50

    摘要： A picture reducing circuit 1 reduces a supplied original picture. A higher picture memory 2 stores an input higher picture. A predictive tap extracting circuit 3 extracts predictive taps from the higher picture stored in the higher picture memory 2 and outputs the extracted predictive taps to a mapping circuit 4, predictive coefficient generating circuit 5, and pixel value updating circuit 8. The mapping circuit 4 calculates a linear combination of predictive taps and predictive coefficients and obtains a predictive picture. The predictive picture is output to an error calculating circuit 6. The error calculating circuit 6 calculates an error (S/N ratio) between pixel value of the predictive picture and that of the original picture. A comparing and determining circuit 7 controls a non-linear processing circuit 9 corresponding to the difference of the errors. The non-linear processing circuit 9 adds or subtracts a predetermined value to/from the pixel value of each pixel of the updated higher picture corresponding to the variation amount of pixel value updated by the pixel value updating circuit 8.

    摘要翻译： 图像缩小电路1减少所提供的原始图像。 较高的图像存储器2存储输入较高的图像。 预测抽头提取电路3从存储在较高画面存储器2中的较高画面提取预测抽头，并将所提取的预测抽头输出到映射电路4，预测系数产生电路5和像素值更新电路8.映射电路4计算 预测抽头和预测系数的线性组合，并获得预测图像。 预测图像被输出到误差计算电路6.误差计算电路6计算预测图像的像素值与原始图像的像素值之间的误差（S / N比）。 比较和确定电路7控制对应于错误差异的非线性处理电路9。 非线性处理电路9对与由像素值更新电路8更新的像素值的变化量相对应的更新后的高级图像的每个像素的像素值加上或减去预定值。

    Nonvolatile semiconductor memory device
    49.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US06243290B1

    公开(公告)日：2001-06-05

    申请号：US09645878

    申请日：2000-08-25

    申请人： Hideaki Kurata ,  Naoki Kobayashi ,  Takashi Kobayashi ,  Katsutaka Kimura ,  Hitoshi Kume ,  Shunichi Saeki

    发明人： Hideaki Kurata ,  Naoki Kobayashi ,  Takashi Kobayashi ,  Katsutaka Kimura ,  Hitoshi Kume ,  Shunichi Saeki

    IPC分类号： G11C1604

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/32 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5623 ,  G11C2211/5624 ,  G11C2211/5642

    摘要： The present invention provides a nonvolatile semiconductor memory device for multilevel data storage that simultaneously carries out programming of multilevel data and subsequent verification at a high programming throughput. For this purpose, the present device includes a circuit 6 to hold programming data when programming is executed, a circuit 7 to generate timing signals to set up level-specific phases of verifying multilevel programming data during a verification period, a circuit 2 to increase stepwise the selected word line voltage during verification in accordance with the above timing signals, a circuit 4 to select target memory cells 1 for verification, depending on the data retrieved from the latch in accordance with the above timing signals, and verify whether the selected memory cells have been programmed on threshold voltage level, according to the energized or de-energized state thereof, and a circuit 5 to supply programming bias to the bit line to program data into insufficiently programmed memory cells, according to the verify results.

    摘要翻译： 本发明提供了一种用于多级数据存储的非易失性半导体存储器件，其以高编程吞吐量同时执行多级数据的编程和后续验证。为此，本设备包括：当执行编程时保存编程数据的电路6， 电路7，用于产生定时信号，以在验证期间建立验证多电平编程数据的电平特定相位;电路2，根据上述定时信号在校验期间逐步增加所选择的字线电压;电路4，用于选择 取决于根据上述定时信号从锁存器检索的数据，并且根据其通电或去激励状态来验证所选择的存储器单元是否已经被设置在阈值电压电平上，以及 一个向位线提供编程偏置以将数据编程为不足的电路5 根据验证结果，编程好的内存单元。