Semiconductor device contact pad and method of contact pad fabrication

    公开(公告)号:US12034027B2

    公开(公告)日:2024-07-09

    申请号:US17408257

    申请日:2021-08-20

    Inventor: Hui Zang

    Abstract: A method for forming a contact pad of a semiconductor device is disclosed. The method includes providing a semiconductor substrate including a first side and a second side. The semiconductor device includes a shallow trench isolation structure, disposed between the first side and the second side, and an intermetal dielectric stack coupled to the second side. The intermetal dielectric stack includes a first metal interconnect. The method further includes etching a first trench into the semiconductor substrate, depositing a dielectric material into the first trench to form a dielectric spacer extending along side walls of the first trench, etching a second trench aligned with the first trench, and depositing a metal material into the second trench to form the contact pad that contacts the first metal interconnect.

    CMOS DEVICES WITH ASYMMETRICALLY PASSIVATED ISOLATION STRUCTURE AND METHODS THEREOF

    公开(公告)号:US20240145512A1

    公开(公告)日:2024-05-02

    申请号:US17975165

    申请日:2022-10-27

    Inventor: Hui Zang

    Abstract: A pixel for an image sensor is described. The pixel comprises a photodiode and an isolation structure disposed within a semiconductor substrate and between a first and second side of the semiconductor substrate. The isolation structure includes a bottom sidewall coupled to a first sidewall and a second sidewall is the isolation structure. The isolation structure is disposed, at least in part, between a gate electrode and the second side of the semiconductor substrate. A first implant region of the semiconductor substrate is disposed proximate to the first sidewall of the isolation. The first implant region is disposed between the photodiode and the first sidewall. A first dopant concentration of the first implant region is greater than a bulk dopant concentration of the semiconductor substrate.

    Pointed-trench pixel-array substrate and associated fabrication method

    公开(公告)号:US11810940B2

    公开(公告)日:2023-11-07

    申请号:US17080797

    申请日:2020-10-26

    Inventor: Hui Zang Gang Chen

    CPC classification number: H01L27/14643 H01L27/14603 H01L31/102

    Abstract: A pointed-trench pixel-array substrate includes a floating diffusion region and a photodiode region formed in a semiconductor substrate. The semiconductor substrate includes, between a top surface and a back surface thereof, a sidewall surface and a bottom surface defining a trench extending into the semiconductor substrate away from a planar region of the top surface surrounding the trench. In a cross-sectional plane perpendicular to the top surface and intersecting the floating diffusion region, the photodiode region, and the trench, (i) the bottom surface is V-shaped and (ii) the trench is located between the floating diffusion region and the photodiode region.

    IMAGE SENSOR DIAGONAL ISOLATION STRUCTURES
    45.
    发明公开

    公开(公告)号:US20230307478A1

    公开(公告)日:2023-09-28

    申请号:US17705133

    申请日:2022-03-25

    CPC classification number: H01L27/1463 H01L27/14629

    Abstract: Image sensors, isolation structures, and techniques of fabrication are provided. An image sensor includes a source of electromagnetic radiation disposed on a substrate, a pixel array disposed on the substrate and thermally coupled with source of electromagnetic radiation, and an isolation structure disposed on the substrate between the source of electromagnetic radiation and the pixel array. The isolation structure can define a first reflective surface oriented on a first bias relative to a lateral axis of the pixel array and a second reflective surface oriented on a second bias relative to the lateral axis. The isolation structure can be configured to attenuate residual electromagnetic radiation reaching a proximal region of the pixel array by pairing a first reflection and a second reflection of the electromagnetic radiation by the first reflective surface and the second reflective surface.

    Flicker-mitigating pixel-array substrate

    公开(公告)号:US11670648B2

    公开(公告)日:2023-06-06

    申请号:US17118230

    申请日:2020-12-10

    Abstract: A flicker-mitigating pixel-array substrate includes a semiconductor substrate and a metal layer. The semiconductor substrate includes a small-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the small-photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the small-photodiode region. The metal layer covers the first back-surface region, at least partially fills the trench, and surrounds the small-photodiode region in the cross-sectional plane. A method for fabricating a flicker-mitigating pixel-array substrate includes forming, on a back surface of a semiconductor substrate, a trench that surrounds a small-photodiode region of the semiconductor substrate in a cross-sectional plane parallel to a first back-surface region of the back surface above the small-photodiode region. The method also includes forming a metal layer on the first back-surface region and in the trench.

    Pyramid-shaped transistors
    47.
    发明授权

    公开(公告)号:US11621336B2

    公开(公告)日:2023-04-04

    申请号:US17326095

    申请日:2021-05-20

    Inventor: Hui Zang Gang Chen

    Abstract: Transistors include a pyramid-shaped gate trench defined by a triangular shape or a trapezoidal shape in a channel width plane and a trapezoidal shape in a channel length plane. Side wall portions of the pyramid-shaped gate trench form a channel having a triangular shape or a trapezoidal shape in the channel width plane. Advantageously, such transistors increase transconductance without increasing pixel width. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

    Uniform threshold voltage non-planar transistors

    公开(公告)号:US11588033B2

    公开(公告)日:2023-02-21

    申请号:US17326112

    申请日:2021-05-20

    Inventor: Hui Zang Gang Chen

    Abstract: Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

    UNIFORM THRESHOLD VOLTAGE NON-PLANAR TRANSISTORS

    公开(公告)号:US20220376069A1

    公开(公告)日:2022-11-24

    申请号:US17326112

    申请日:2021-05-20

    Inventor: Hui Zang Gang Chen

    Abstract: Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

    PROCESS TO RELEASE SILICON STRESS IN FORMING CMOS IMAGE SENSOR

    公开(公告)号:US20220359581A1

    公开(公告)日:2022-11-10

    申请号:US17307789

    申请日:2021-05-04

    Abstract: Process to release Silicon stress in forming CMOS image sensor. In one embodiment, a method for manufacturing an image sensor includes providing a first wafer that is a semiconductor substrate, where the first wafer has a first side and a second side opposite from the first side. The method also includes attaching a second wafer to the second side of the first wafer. The method further includes forming isolation structures in the second wafer by etching. The isolation structures are bounded by the second side of the first wafer. The method also includes growing an epitaxial layer between individual isolation structures.

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