公开(公告)号：US20190332153A1

公开(公告)日：2019-10-31

申请号：US15965963

申请日：2018-04-29

Applicant: Oracle International Corporation

Inventor： Lin Zhang ,  Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/28 ,  G06F1/08

Abstract: A method for determining power dissipation within a computer system is disclosed. A circuit block may receive a regulated voltage level on a power supply signal generated by a voltage regulator circuit. A power control circuit may measure a current drawn by the circuit block, and determine a real-time voltage level for the power supply signal using the current and based on a slope value and a zero-load voltage level. Additionally, power control circuit may determine a power dissipation for the circuit block using the current and the real-time voltage level, and adjust an operation parameter of the circuit block based on the power dissipation.

公开(公告)号：US10365698B2

公开(公告)日：2019-07-30

申请号：US15661372

申请日：2017-07-27

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/32 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3296

Abstract: A power management controller is disclosed. Broadly speaking, the controller may, in response to receiving a timing signal, monitor a temperature of an integrated circuit including multiple processor clusters. The controller may generate a comparison of the temperature and a threshold value, and in response to a determination that the comparison indicates that the temperature is less than the threshold value, transition a particular processor cluster to a new power state.

公开(公告)号：US20190033931A1

公开(公告)日：2019-01-31

申请号：US15661372

申请日：2017-07-27

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/20 ,  G06F1/32

CPC classification number: G06F1/206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296

Abstract: A power management controller is disclosed. Broadly speaking, the controller may, in response to receiving a timing signal, monitor a temperature of an integrated circuit including multiple processor clusters. The controller may generate a comparison of the temperature and a threshold value, and in response to a determination that the comparison indicates that the temperature is less than the threshold value, transition a particular processor cluster to a new power state.

公开(公告)号：US09312864B2

公开(公告)日：2016-04-12

申请号：US14498744

申请日：2014-09-26

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols ,  Changku Hwang ,  Daniel S. Woo

IPC: H03K3/03 ,  H03L7/08 ,  H03L7/099 ,  H03L7/00

CPC classification number: H03L7/0802 ,  H03L7/00 ,  H03L7/07 ,  H03L7/08 ,  H03L7/099 ,  H03L7/0991

Abstract: In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.

Abstract translation: 在提供时钟信号的集成电路中，非对称频率锁相环（AFLL）包括输出具有第一基频的第一信号的第一数字控制振荡器（DCO）和输出具有第一基频的第二信号的第二DCO， 第二基频。 集成电路包括向第二DCO提供电源电压的电压调节器。 此外，AFLL包括基于电源电压和平均电源电压的瞬时值来选择第一DCO和第二DCO中的一个的控制逻辑。 此外，AFLL基于电源电压的瞬时值和平均电源电压来调整第一子锁频环路中所选DCO的增益。 以这种方式，降低了集成电路中电源电压变化对时间关键路径的影响。

公开(公告)号：US20150370303A1

公开(公告)日：2015-12-24

申请号：US14308079

申请日：2014-06-18

Applicant: Oracle International Corporation

Inventor： Venkatram Krishnaswamy ,  Georgios K. Konstadinidis ,  Sebastian Turullols ,  Yifan YangGong

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3243 ,  Y02D10/126 ,  Y02D10/152

Abstract: A system includes a power management unit that may monitor the power consumed by a processor including a plurality of processor core. The power management unit may throttle or reduce the operating frequency of the processor cores by applying a number of throttle events in response to determining that the plurality of cores is operating above a predetermined power threshold during a given monitoring cycle. The number of throttle events may be based upon a relative priority of each of the plurality of processor cores to one another and an amount that the processor is operating above the predetermined power threshold. The number of throttle events may correspond to a portion of a total number of throttle events, and which may be dynamically determined during operation based upon a proportionality constant and the difference between the total power consumed by the processor and a predetermined power threshold.

Abstract translation: 一种系统包括能够监视包括多个处理器核心的处理器消耗的功率的电力管理单元。 电源管理单元可以通过施加多个节气门事件来响应于在给定的监视循环期间确定多个核在高于预定功率阈值的情况下运行，来节流或降低处理器核心的工作频率。 油门事件的数量可以基于多个处理器核心中的每一个相对于彼此的相对优先级，以及处理器在高于预定功率阈值的情况下操作的量。 节气门事件的数量可以对应于节气门事件总数的一部分，并且其可以在操作期间基于比例常数和处理器消耗的总功率与预定功率阈值之间的差异来动态地确定。

公开(公告)号：US20150365093A1

公开(公告)日：2015-12-17

申请号：US14498744

申请日：2014-09-26

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols ,  Changku Hwang ,  Daniel S. Woo

IPC: H03L7/08 ,  H03L7/099

CPC classification number: H03L7/0802 ,  H03L7/00 ,  H03L7/07 ,  H03L7/08 ,  H03L7/099 ,  H03L7/0991

Abstract: In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.

Abstract translation: 在提供时钟信号的集成电路中，非对称频率锁相环（AFLL）包括输出具有第一基频的第一信号的第一数字控制振荡器（DCO）和输出具有第一基频的第二信号的第二DCO， 第二基频。 集成电路包括向第二DCO提供电源电压的电压调节器。 此外，AFLL包括基于电源电压和平均电源电压的瞬时值来选择第一DCO和第二DCO中的一个的控制逻辑。 此外，AFLL基于电源电压的瞬时值和平均电源电压来调整第一子锁频环路中所选DCO的增益。 以这种方式，降低了集成电路中电源电压变化对时间关键路径的影响。

公开(公告)号：US20150347666A1

公开(公告)日：2015-12-03

申请号：US14293763

申请日：2014-06-02

Applicant: Oracle International Corporation

Inventor： Haowei Zhang ,  Xiaoying Shen ,  Sebastian Turullols

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/11 ,  G06F17/16 ,  G06F17/5009 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/84 ,  G06F2217/86

Abstract: Embodiments include systems and methods for optimization of micro-benchmark analysis for microprocessor designs. For example, embodiments seek to generate a suite of micro-benchmarks and associated weighting factors, which can be used to effectively define a weighted aggregate workload condition for a fine-grained (e.g., RTL) simulation in a manner that is a sufficient proxy for predicted commercial workload conditions. The suite of micro-benchmarks can be appreciably more efficient to simulate than the commercial workload, so that using the suite of micro-benchmarks as a proxy for the commercial workload can provide many benefits, including more efficient iterative design.

Abstract translation: 实施例包括用于优化微处理器设计的微基准分析的系统和方法。 例如，实施例寻求生成一组微基准和相关联的加权因子，其可以用于以对于细粒度（例如，RTL）模拟）有效地定义加权聚合工作负载条件，其方式是足够的代理 预测商业工作量情况。 微型基准测试套件可以比商业工作量更高效地模拟，因此使用微型基准套件作为商业工作负载的代理可以提供许多好处，包括更有效的迭代设计。

公开(公告)号：US20140095909A1

公开(公告)日：2014-04-03

申请号：US13631296

申请日：2012-09-28

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Sebastian Turullols

IPC: G06F1/32 ,  G06F1/06

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  H03K17/16 ,  Y02D10/126

Abstract: Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals that include a skipped clock cycle to a portion of a computing system. The skipped cycle clock signals may be changed by the computing system during operation of the system by altering masks applied to a global clock signal. However, the flexibility to alter various skipped cycle clock signals may introduce noise or signal disruptions within the system. Thus, the present disclosure may also involve an apparatus and/or method for managing the altering of the clock cycle skipping masks to manage the voltage noise introduced into the system by the adjustment of the operating frequency of the portions of the system. In one embodiment, the method includes prioritizing or otherwise ordering the bits of the masks applied to the global clock signal to attempt to prevent similar bits from being altered simultaneously.

Abstract translation: 本公开的实现涉及用于向计算系统的一部分提供包括跳过的时钟周期的一个或多个时钟信号的装置和/或方法。 跳过的周期时钟信号可以由系统操作期间的计算系统通过改变施加到全局时钟信号的掩码来改变。 然而，改变各种跳过周期时钟信号的灵活性可能在系统内引入噪声或信号中断。 因此，本公开还可以涉及用于管理改变时钟周期跳过掩码以通过调整系统的部分的操作频率来管理引入到系统中的电压噪声的装置和/或方法。 在一个实施例中，该方法包括将应用于全局时钟信号的掩码的比特优先化或以其他方式排序，以试图防止同时改变类似的比特。