-
公开(公告)号：US20110040995A1
公开(公告)日：2011-02-17
申请号：US12539978
申请日：2009-08-12
申请人： Jayanta Basak , Pradip Bose , Alper Buyuktosunoglu , Anita Lungu
发明人： Jayanta Basak , Pradip Bose , Alper Buyuktosunoglu , Anita Lungu
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： A mechanism is provided for predictively power gating a set of units within the data processing system. A second-level power gating controller monitors a set of events for each unit in a set of units within the data processing system. The second-level power gating controller identifies idle sequences of a predetermined set of cycles within the events from each unit where the unit is idle. The second-level power gating controller determines preceding sequences of a predetermined length that precede the idle sequences. The second-level power gating controller determines an accuracy of the preceding sequences. Responsive to the accuracy being above a threshold, the second-level power gating controller sends a permit command to a first-level power gating mechanism associated with the unit to permit power gating of the unit.
摘要翻译： 提供了用于在数据处理系统内预测性地选通一组单元的机构。 二级电源门控控制器监视数据处理系统内的一组单元中的每个单元的一组事件。 第二级电力门控控制器从单元空闲的每个单元的事件内识别预定的一组周期的空闲序列。 第二级电源门控控制器确定在空闲序列之前的预定长度的先前序列。 二级电源门控控制器确定前面的序列的精度。 响应于精度高于阈值，二级电源门控控制器向与该单元相关联的一级电源门控机构发送允许命令，以允许该单元的电源门控。
-
公开(公告)号：US07865747B2
公开(公告)日：2011-01-04
申请号：US09971186
申请日：2001-10-05
申请人： Alper Buyuktosunoglu , Stanley E. Schuster , David M. Brooks , Pradip Bose , Peter W. Cook , David H. Albonesi
发明人： Alper Buyuktosunoglu , Stanley E. Schuster , David M. Brooks , Pradip Bose , Peter W. Cook , David H. Albonesi
IPC分类号： G06F1/32
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/329 , G06F9/3802 , G06F9/3814 , Y02D10/24
摘要： A method and structure of reducing power consumption in a microprocessor includes at least one storage structure in which the activity of the storage structure is dynamically measured and the size of the structure is controlled based on the activity. The storage structure includes a plurality of blocks, and the size of the structure is controlled in units of block size, based on activity measured in the blocks. An exemplary embodiment is an adaptive out-of-order queue.
摘要翻译： 降低微处理器功耗的方法和结构包括至少一个存储结构，其中动态地测量存储结构的活动，并且基于活动来控制结构的大小。 存储结构包括多个块，并且基于块中测量的活动，以块大小为单位来控制结构的大小。 示例性实施例是自适应失序队列。
-
43.发明申请METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT 有权通过自动基于方法的控制和管理，峰值功率执行的方法和系统公开(公告)号：US20090089602A1
公开(公告)日：2009-04-02
申请号：US11862559
申请日：2007-09-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/28
CPC分类号： G06F1/3287 , G06F1/206 , G06F9/3836 , G06F9/3869 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D50/20
摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.
摘要翻译： 一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令 状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间 间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率 基于系统中分配的令牌总数的消耗限制。
-
44.发明申请METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT 失效通过功率性能监视器和控制单元控制芯片中的功率的方法和系统公开(公告)号：US20090049318A1
公开(公告)日：2009-02-19
申请号：US12132044
申请日：2008-06-03
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。
-
公开(公告)号：US09043626B2
公开(公告)日：2015-05-26
申请号：US13529161
申请日：2012-06-21
申请人： Pradip Bose , Alper Buyuktosunoglu , Dilma Menezes Da Silva , Hubertus Franke , Priyanka Tembey
发明人： Pradip Bose , Alper Buyuktosunoglu , Dilma Menezes Da Silva , Hubertus Franke , Priyanka Tembey
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/3203 , G06F1/329 , G06F9/4893 , G06F9/50 , Y02D10/24
摘要： Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.
摘要翻译： 通过设置执行多线程应用程序的多核微处理器平台消耗的功耗的峰值功率级别来管理微处理器平台中的功耗。 多核微处理器平台包含多个物理核，每个物理核可配置成多个逻辑核。 响应于多核微处理器平台的功率消耗水平超过峰值功率水平，通过改变该物理核心上的逻辑核心数来调整至少一个物理核心中的同时多线程级别。 基于同步多线程级别的性能和功耗数据用于选择要调整的物理内核。
-
46.发明授权Current-aware floorplanning to overcome current delivery limitations in integrated circuits 有权电流识别布局规划，以克服集成电路中的当前传输限制公开(公告)号：US08863068B2
公开(公告)日：2014-10-14
申请号：US13526194
申请日：2012-06-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/50 , G06F2217/78
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
-
47.发明授权Token-based current control to mitigate current delivery limitations in integrated circuits 有权基于令牌的电流控制，以减轻集成电路中的当前传输限制公开(公告)号：US08826216B2
公开(公告)日：2014-09-02
申请号：US13526153
申请日：2012-06-18
CPC分类号： G06F17/5054 , G06F9/455 , G06F9/46 , G06F9/5044 , G06F15/177 , G06F17/5022 , G06F17/5045 , G06F2212/1041 , G06F2217/78
摘要： A system and method of operating an integrated circuit (IC) having a fixed layout of one or more blocks having one or more current sources therein that draw electrical current from a power source. The method includes dynamically issuing to a block configured to perform operations responsive to an instruction received at the block, a reserve amount of tokens; determining for each issuance of instruction to the block whether that block's reserve token amount exceeds zero; and one of: issuing the instruction to the block if the token reserve for that block is greater than one, and decrementing, after issuance of the instruction, by one token the block's reserve token amount, or, preventing issuance of an instruction to the block. In the method, each block may be initialized to have: a reserve token amount of zero, a token expiration period; a token generation cycle and a token generation amount.
摘要翻译： 一种具有固定布局的集成电路（IC）的系统和方法，所述集成电路（IC）具有一个或多个具有一个或多个电流源的块，其中所述一个或多个块来自电源。 所述方法包括动态地发布到被配置为响应于在所述块处接收的指令执行操作的块，标记的保留量; 确定每个向块的指令的发出是否该块的储备标记量超过零; 其中之一是：如果该块的令牌保留大于1，则向块发出指令，并且在发出指令之后递减一个令牌块的保留令牌量，或者阻止向块发出指令 。 在该方法中，每个块可以被初始化为具有：保留令牌量为零，令牌到期期间; 令牌生成周期和令牌生成量。
-
48.发明授权Virtualized abstraction with built-in data alignment and simultaneous event monitoring in performance counter based application characterization and tuning 有权虚拟化抽象与基于性能计数器的应用程序表征和调优内置数据对齐和同时事件监视公开(公告)号：US08798962B2
公开(公告)日：2014-08-05
申请号：US13052616
申请日：2011-03-21
申请人： Pradip Bose , Alper Buyuktosunoglu , Canturk Isci , Jeff Kephart , Xiaoqiao Meng , Ruhi Sarikaya
发明人： Pradip Bose , Alper Buyuktosunoglu , Canturk Isci , Jeff Kephart , Xiaoqiao Meng , Ruhi Sarikaya
CPC分类号： G06F11/3089 , G06F11/3024 , G06F11/3466 , G06F2201/815 , G06F2201/86 , G06F2201/88
摘要： Techniques for monitoring a set of one or more event counters of application execution are provided. The techniques include constructing a virtual performance monitoring counter (VPMC) layer as a unified abstraction of a physical performance monitoring counter (PMC) architecture, and incorporating one or more programming interfaces (PIs) in connection with the virtual performance monitoring counter, wherein the one or more programming interfaces facilitate simultaneous access and data monitoring across a set of one or more event counters.
摘要翻译： 提供了用于监视应用执行的一个或多个事件计数器的集合的技术。 这些技术包括构建虚拟性能监视计数器（VPMC）层作为物理性能监视计数器（PMC）体系结构的统一抽象，并且结合一个或多个与虚拟性能监视计数器结合的编程接口（PI），其中一个 或更多的编程接口便于跨一组或多个事件计数器的同时访问和数据监视。
-
49.发明授权Adaptive workload based optimizations to mitigate current delivery limitations in integrated circuits 有权基于自适应工作负载的优化，以减轻集成电路中的当前传输限制公开(公告)号：US08683418B2
公开(公告)日：2014-03-25
申请号：US13526230
申请日：2012-06-18
CPC分类号： H01L23/00 , G06F11/00 , G06F11/3062 , H01L23/50 , H01L25/065 , H01L2224/16145 , H01L2224/16225
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前的交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
-
50.发明申请公开(公告)号：US20140082580A1
公开(公告)日：2014-03-20
申请号：US13526194
申请日：2012-06-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/50 , G06F2217/78
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前的交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
-
-
-
-
-
-
-
-
-
搜索结果
112 条记录 (耗时 0.023 秒)
