公开(公告)号：US20120256270A1

公开(公告)日：2012-10-11

申请号：US13525840

申请日：2012-06-18

申请人： Byoung H. Lee ,  Sang Ho Bae ,  Kisik Choi ,  Rino Choi ,  Craig Huffman ,  Prashant Majhi ,  Jong Hoan Sim ,  Seung-Chul Song ,  Zhibo Zhang

发明人： Byoung H. Lee ,  Sang Ho Bae ,  Kisik Choi ,  Rino Choi ,  Craig Huffman ,  Prashant Majhi ,  Jong Hoan Sim ,  Seung-Chul Song ,  Zhibo Zhang

IPC分类号： H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517

摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.

摘要翻译： 公开了形成双金属栅极和形成的栅极的方法。 一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属的功函数 层（形成PMOS金属）。 该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。 由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

公开(公告)号：US20110121266A1

公开(公告)日：2011-05-26

申请号：US13017862

申请日：2011-01-31

申请人： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

发明人： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC分类号： H01L29/06 ,  H01L21/20

CPC分类号： H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

摘要翻译： 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US07696517B2

公开(公告)日：2010-04-13

申请号：US12054597

申请日：2008-03-25

申请人： Hongfa Luan ,  Prashant Majhi

发明人： Hongfa Luan ,  Prashant Majhi

IPC分类号： H01L31/112 ,  H01L27/108 ,  H01L29/00

CPC分类号： H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/78

摘要： Transistors having a Hafnium-Silicon gate electrode and high-k dielectric are disclosed. A workpiece is provided having a gate dielectric formed over the workpiece, and a gate formed over the gate dielectric. The gate may comprise a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.

摘要翻译： 公开了具有铪硅栅电极和高k电介质的晶体管。 提供了具有形成在工件上的栅极电介质的工件和形成在栅极电介质上的栅极。 栅极可以包括Hf和Si的组合层。 栅极的Hf和Si的组合层建立了晶体管的阈值电压Vt。 晶体管可以包括CMOS器件的单个NMOS晶体管或NMOS晶体管。

公开(公告)号：US20090039441A1

公开(公告)日：2009-02-12

申请号：US11837161

申请日：2007-08-10

申请人： Hongfa Luna ,  Kisik Choi ,  Prashant Majhi ,  Husam Alshareef ,  Huang-Chun Wen ,  Rusty Harris ,  Byoung Hun Lee

发明人： Hongfa Luna ,  Kisik Choi ,  Prashant Majhi ,  Husam Alshareef ,  Huang-Chun Wen ,  Rusty Harris ,  Byoung Hun Lee

IPC分类号： H01L27/08 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517

摘要： Devices comprising, and method for fabricating, a MOSFET with a metal gate electrode are disclosed. In one embodiment, the MOSFET includes a first doped region configured to receive current from a current source, a second doped region configured to drain current from the first doped region when an electric field is modified between the first doped region and the second doped region, and a gate electrode configured to modify the electric field. The gate electrode may include a high-k layer, a hafnium-based metal layer formed above the high-k layer, and a polysilicon layer formed above the hafnium-based metal layer. In a further embodiment, the gate electrode further comprises a titanium-based metal layer formed between the hafnium-based metal layer and the polysilicon layer.

摘要翻译： 公开了包括用于制造具有金属栅电极的MOSFET的器件及其制造方法。 在一个实施例中，MOSFET包括被配置为从电流源接收电流的第一掺杂区域，被配置为当在第一掺杂区域和第二掺杂区域之间修改电场时从第一掺杂区域漏极电流的第二掺杂区域， 以及构造成修改电场的栅电极。 栅电极可以包括形成在高k层上方的高k层，铪基金属层和形成在铪基金属层上方的多晶硅层。 在另一实施例中，栅电极还包括在铪基金属层和多晶硅层之间形成的钛基金属层。

公开(公告)号：US20080164536A1

公开(公告)日：2008-07-10

申请号：US12054597

申请日：2008-03-25

申请人： Hongfa Luan ,  Prashant Majhi

发明人： Hongfa Luan ,  Prashant Majhi

IPC分类号： H01L29/423

CPC分类号： H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/78

摘要： Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si). The gate may comprise a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.

摘要翻译： 公开了晶体管及其制造方法。 提供工件，在工件上形成栅极电介质，并且通过将工件暴露于铪（Hf）的前体和硅（Si）的前体，在栅极电介质上形成栅极。 栅极可以包括Hf和Si的组合层。 栅极的Hf和Si的组合层建立了晶体管的阈值电压V SUB。 晶体管可以包括CMOS器件的单个NMOS晶体管或NMOS晶体管。

公开(公告)号：US07256056B2

公开(公告)日：2007-08-14

申请号：US10552950

申请日：2004-04-14

申请人： Prashant Majhi

发明人： Prashant Majhi

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G01B7/06

摘要： The method for determining the thickness of a dielectric layer according to the invention comprises the step of providing an electrically conductive body (11) having a dielectric layer (13) which is separated from the electrically conductive body (11) by at least a further dielectric layer (3) and a surface (15) of which is exposed. Onto the exposed surface (15) an electric charge is deposited, thereby inducing an electric potential difference between the exposed surface (15) and the electrically conductive body (11). An electrical parameter relating to the electric potential difference is determined and a measurement is performed to obtain additional measurement data relating to the thickness of the dielectric layer (13) and/or to the thickness of the further dielectric layer (3). In this way the thickness of the dielectric layer (13) and/or of the further dielectric layer (3) is determined. The method of manufacturing an electric device (100) comprises this method for determining the thickness of a dielectric layer. The apparatus (10) for determining the thickness of a dielectric layer is arranged to execute this method.

摘要翻译： 根据本发明的用于确定电介质层的厚度的方法包括提供具有电介质层（13）的导电体（11）的步骤，所述电介质层通过至少另外的电介质（13）与导电体（11）分离， 层（3）和其表面（15）暴露。 在暴露表面（15）上沉积电荷，从而在暴露表面（15）和导电体（11）之间产生电位差。 确定与电位差有关的电参数，并进行测量以获得与介电层（13）的厚度和/或另外的电介质层（3）的厚度有关的附加测量数据。 以这种方式确定电介质层（13）和/或另外的电介质层（3）的厚度。 制造电气设备（100）的方法包括用于确定电介质层的厚度的方法。 用于确定电介质层的厚度的装置（10）被布置成执行该方法。

公开(公告)号：US20070063296A1

公开(公告)日：2007-03-22

申请号：US11233356

申请日：2005-09-22

申请人： Kisik Choi ,  Husam Alshareef ,  Prashant Majhi

发明人： Kisik Choi ,  Husam Alshareef ,  Prashant Majhi

IPC分类号： H01L29/94

CPC分类号： H01L21/823842

摘要： Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where the second metal layer modulated the work function of the first metal layer. The second metal layer and subsequently etch, exposing a portion of the first metal layer. A third metal layer may be deposited on the etched second metal layer and the exposed first metal layer, where the third metal layer may modulate the work function of the exposed first metal layer. Subsequent fabrication techniques were used to define the gate stack.

摘要翻译： 提供了用于制造用于互补金属氧化物半导体（CMOS）器件的具有不同功函数的两个金属栅极叠层的方法。第一金属层可沉积在栅极电介质上，随后沉积第二金属层，其中第二金属层调制 第一金属层的功函数。 第二金属层并随后蚀刻，暴露第一金属层的一部分。 可以在蚀刻的第二金属层和暴露的第一金属层上沉积第三金属层，其中第三金属层可以调节暴露的第一金属层的功函数。 使用随后的制造技术来定义栅极堆叠。

公开(公告)号：US20060214680A1

公开(公告)日：2006-09-28

申请号：US10552950

申请日：2004-04-14

申请人： Prashant Majhi

发明人： Prashant Majhi

IPC分类号： G01R31/26

CPC分类号： G01B7/06

摘要： The method for determining the thickness of a dielectric layer according to the invention comprises the step of providing an electrically conductive body (11) having a dielectric layer (13) which is separated from the electrically conductive body (11) by at least a further dielectric layer (3) and a surface (15) of which is exposed. Onto the exposed surface (15) an electric charge is deposited, thereby inducing an electric potential difference between the exposed surface (15) and the electrically conductive body (11). An electrical parameter relating to the electric potential difference is determined and a measurement is performed to obtain additional measurement data relating to the thickness of the dielectric layer (13) and/or to the thickness of the further dielectric layer (3). In this way the thickness of the dielectric layer (13) and/or of the further dielectric layer (3) is determined. The method of manufacturing an electric device (100) comprises this method for determining the thickness of a dielectric layer. The apparatus (10) for determining the thickness of a dielectric layer is arranged to execute this method.

摘要翻译： 根据本发明的用于确定电介质层的厚度的方法包括提供具有电介质层（13）的导电体（11）的步骤，所述电介质层通过至少另外的电介质（13）与导电体（11）分离， 层（3）和其表面（15）暴露。 在暴露表面（15）上沉积电荷，从而在暴露表面（15）和导电体（11）之间产生电位差。 确定与电位差有关的电参数，并进行测量以获得与介电层（13）的厚度和/或另外的电介质层（3）的厚度有关的附加测量数据。 以这种方式确定电介质层（13）和/或另外的电介质层（3）的厚度。 制造电气设备（100）的方法包括用于确定电介质层的厚度的方法。 用于确定电介质层的厚度的装置（10）被布置成执行该方法。

公开(公告)号：US20190043882A1

公开(公告)日：2019-02-07

申请号：US16021550

申请日：2018-06-28

申请人： Khaled Hasnat ,  Prashant Majhi ,  Krishna Parat

发明人： Khaled Hasnat ,  Prashant Majhi ,  Krishna Parat

IPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L23/532 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L29/51

摘要： Embodiments of the present disclosure are directed towards techniques to provide a memory device with reduced capacitance. In one embodiment, a memory array is formed in a die, and includes one or more pillars and a plurality of wordlines coupled with the one or more pillars. Adjacent wordlines of the plurality of wordlines are separated by respective dielectric layers, which may include components, to reduce capacitance of the plurality of wordlines. The components comprise air gaps or low-k dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US09559215B1

公开(公告)日：2017-01-31

申请号：US14757875

申请日：2015-12-23

申请人： Khaled Ahmed ,  Prashant Majhi

发明人： Khaled Ahmed ,  Prashant Majhi

IPC分类号： H01L29/786 ,  H01L29/12 ,  H01L29/24 ,  H01L21/02 ,  H01L21/425 ,  H01L21/477 ,  H01L21/385 ,  H01L29/66 ,  H01L27/12

CPC分类号： H01L29/78696 ,  H01L21/02565 ,  H01L21/02584 ,  H01L21/02631 ,  H01L21/385 ,  H01L21/425 ,  H01L21/477 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/247 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

摘要： Embodiments of the invention include sulfur alloyed InGaZnO (IGZOS) thin film transistors (TFTs) and methods of making such devices. In one embodiment, the IGZOS TFT may include a substrate and a gate electrode formed over the substrate. A gate dielectric layer may be formed over the gate electrode. An IGZOS film may be formed over a surface of the gate dielectric. Additionally, embodiments of the invention include a source region and a drain region formed in contact with the IGZOS film. An opening between the source region and the drain region may define a channel region in the IGZOS film. Embodiments of the invention are able to form a p-type IGZO TFT by increasing the valence band of the IGZO material in order to eliminate the presence of trap states in the band gap. The valance band may be raised by doping the IGZO material with sulfur.

摘要翻译： 本发明的实施例包括硫合金InGaZnO（IGZOS）薄膜晶体管（TFT）以及制造这种器件的方法。 在一个实施例中，IGZOS TFT可以包括衬底和形成在衬底上的栅电极。 栅电介质层可以形成在栅电极上。 可以在栅极电介质的表面上形成IGZOS膜。 另外，本发明的实施例包括形成为与IGZOS膜接触的源极区域和漏极区域。 源极区域和漏极区域之间的开口可以限定IGZOS膜中的沟道区域。 本发明的实施例能够通过增加IGZO材料的价带形成p型IGZO TFT，以消除带隙中陷阱状态的存在。 可以通过用硫掺杂IGZO材料来提高价带。