公开(公告)号：US09841940B2

公开(公告)日：2017-12-12

申请号：US14731499

申请日：2015-06-05

Applicant: QUALCOMM Incorporated

Inventor： Alexander Khazin ,  Lior Amarilio

IPC: G06F17/00 ,  G06F3/16 ,  G06F1/08 ,  G06F1/32 ,  H04R3/00 ,  G11B27/30

CPC classification number: G06F3/165 ,  G06F1/08 ,  G06F1/324 ,  G11B27/3036 ,  H04R3/00 ,  H04R2460/03 ,  Y02D10/126

Abstract: Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.

公开(公告)号：US20160062729A1

公开(公告)日：2016-03-03

申请号：US14842451

申请日：2015-09-01

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Aris Balatsos

IPC: G06F3/16 ,  G06F13/42 ,  G06F13/28 ,  H04S3/00

CPC classification number: G06F3/162 ,  G06F13/28 ,  G06F13/287 ,  G06F13/4282 ,  H04S3/008

Abstract: Multi-channel audio communication in a Serial Low-power Inter-chip Media Bus (SLIMbus) system is disclosed. In this regard, in one aspect, a multi-channel output port is provided in a SLIMbus system. The multi-channel output port receives an audio stream from an audio source (e.g., a storage medium) via a direct memory access (DMA) pipe and distributes the audio stream to multiple receiving ports (e.g., speakers) over multiple data channels, all connected to the single multi-channel output port. In another aspect, a multi-channel input port is provided in a SLIMbus system. The multi-channel input port connects to multiple data channels from multiple distributing ports (e.g., microphones). By providing the multi-channel output port and/or the multi-channel input port in a SLIMbus system, it is possible to support multiple data channels with a single DMA pipe, thus improving implementation flexibilities and efficiencies of the SLIMbus system.

Abstract translation: 公布了串行低功率片上媒体总线（SLIMbus）系统中的多声道音频通信。 在这方面，在一个方面，在SLIMbus系统中提供多通道输出端口。 多通道输出端口通过直接存储器访问（DMA）管道从音频源（例如，存储介质）接收音频流，并且通过多个数据信道将音频流分配到多个接收端口（例如，扬声器），全部 连接到单个多通道输出端口。 另一方面，在SLIMbus系统中提供多通道输入端口。 多通道输入端口从多个分配端口（例如麦克风）连接到多个数据通道。 通过在SLIMbus系统中提供多通道输出端口和/或多通道输入端口，可以使用单个DMA管道支持多个数据通道，从而提高SLIMbus系统的实施灵活性和效率。

公开(公告)号：US20150371690A1

公开(公告)日：2015-12-24

申请号：US14722291

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Alexander Khazin

IPC: G11C7/10 ,  G06F13/28 ,  G06F13/364 ,  G06F13/40 ,  G06F13/42

CPC classification number: G11C7/1075 ,  G06F13/287 ,  G06F13/364 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4282 ,  G06F13/4295 ,  G11C7/1036

Abstract: Time-constrained data copying between storage media is disclosed. When an electronic device is engaged in real-time operations, multiple data blocks may need to be copied from one storage medium to another storage medium within certain time constraints. In this regard, a data port is operatively controlled by a plurality of registers of a first register bank. The plurality of registers is copied from the first register bank to a second register bank within a temporal limit and while the data port remains under control of the plurality of registers being copied. By copying the plurality of registers within the temporal limit, it is possible to prevent operational interruption in the data port and reduce bandwidth overhead associated with the register copying operation.

Abstract translation: 公开了存储介质之间的时间受限的数据复制。 当电子设备进行实时操作时，在某些时间限制内可能需要将多个数据块从一个存储介质复制到另一个存储介质。 在这方面，数据端口由第一寄存器组的多个寄存器可操作地控制。 多个寄存器在时间限制内从第一寄存器组复制到第二寄存器组，同时数据端口仍然被复制的多个寄存器的控制。 通过在时间限制内复制多个寄存器，可以防止数据端口中的操作中断，并减少与寄存器复制操作相关联的带宽开销。

公开(公告)号：US20220129398A1

公开(公告)日：2022-04-28

申请号：US17082873

申请日：2020-10-28

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Lior Amarilio ,  Sharon Graif

IPC: G06F13/20 ,  G06F13/42

Abstract: Tunneling over Universal Serial Bus (USB) sideband channel systems and methods provide a way to tunnel I2C transactions between a master and slaves over USB 4.0 sideband channels. More particularly, a slave address table lookup (SATL) circuit is added to a host circuit. Signals from an I2C bus are received at the host, and any address associated with a destination is translated by the SATL. The translated address is passed to a low-speed interface associated with a sideband channel in the host circuit. Signals received at the low-speed interface are likewise reverse translated in the SATL and then sent out through the I2C bus. In this fashion, low-speed I2C signals may be routed over the sideband channel through the low-speed sideband interface portion of the USB interface.

公开(公告)号：US10733121B2

公开(公告)日：2020-08-04

申请号：US16392264

申请日：2019-04-23

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt ,  Sharon Graif ,  Lior Amarilio ,  Kishalay Haldar ,  Oren Nishry

IPC: G06F9/455 ,  G06F13/20 ,  G06F13/42

Abstract: Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.

公开(公告)号：US10678723B2

公开(公告)日：2020-06-09

申请号：US16134559

申请日：2018-09-18

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Lior Amarilio ,  Mark Gakman

IPC: G06F13/24 ,  G06F13/362 ,  G06F13/42

Abstract: Systems, methods, and apparatus are described that enable communication of in-band reset signals over an I3C serial bus. A method performed at a slave device includes driving a data line of the I3C serial bus from a high state to a low state before a first clock pulse is received from a clock line of the I3C serial bus after a start condition has been provided on the I3C serial bus, where driving the data line from the high state to the low state produces an initial pulse on the data line, transmitting one or more additional pulses on the data line before the first clock pulse is transmitted on the clock line, and driving the data line low until a rising edge of the first clock pulse is detected on the clock line after each of the plurality of additional pulses has been successfully transmitted on the data line.

公开(公告)号：US10560780B2

公开(公告)日：2020-02-11

申请号：US16260325

申请日：2019-01-29

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Ghanashyam Prabhu ,  Sharon Graif ,  Mouna Elkhatib

IPC: H04B3/00 ,  H04R3/12 ,  G06F3/16 ,  H04R5/04 ,  H04R3/00 ,  G06F13/42

Abstract: Exemplary aspects of the present disclosure assist in phase alignment for systems having multiple audio sources. For example, in a system having plural microphones, phase alignment may also be assisted by sampling the microphones at the appropriate time relative to when the samples are placed on the audio bus. Further, phase shifts between audio samples are reduced or eliminated by keeping a sample delay constant for samples from the same microphone. Such manipulation of the audio samples reduces phase shifts which reduces the likelihood of an audio artifact capable of being detected by the human ear and thus improves consumer experience.

公开(公告)号：US10511397B2

公开(公告)日：2019-12-17

申请号：US15878790

申请日：2018-01-24

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Sharon Graif ,  Lalan Jee Mishra

IPC: H04J3/02 ,  G06F3/16 ,  G06F13/42 ,  H04L12/40 ,  H04B1/38

Abstract: Systems and methods for providing virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus are disclosed. While a SOUNDWIRE bus is particularly contemplated, other TDM buses may also be used to provide the benefits outlined herein. In particular, raw GPIO signals are placed into time slots on a TDM bus without requiring additional overhead or packaging. This arrangement allows all drops on a multi-drop bus to receive the GPIO signals substantially concurrently with latency measured in less than a frame period.

公开(公告)号：US10419852B2

公开(公告)日：2019-09-17

申请号：US15894401

申请日：2018-02-12

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Amit Gil ,  Oded Schnitzer

IPC: H04R3/00 ,  G10L19/012 ,  G06F3/16 ,  H03G3/34 ,  G10L19/16 ,  G06F13/38

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

公开(公告)号：US10261569B2

公开(公告)日：2019-04-16

申请号：US14702175

申请日：2015-05-01

Applicant: QUALCOMM Incorporated

Inventor： Nir Gerber ,  Lior Amarilio ,  Amit Gil

IPC: G06F1/32 ,  G06F1/26 ,  G06F1/3234 ,  G06F13/38

Abstract: Aspects disclosed in the detailed description include scheduled universal serial bus (USB) low-power operations. In this regard, in one aspect, a USB host controller determines a low-power operation schedule for a USB client device. The low-power operation schedule comprises one or more scheduled low-power operation periods, each corresponding to a respective entry time and a respective exit time. The USB host controller communicates the low-power operation schedule to the USB client device using one or more USB standard packets. By scheduling the one or more scheduled low-power operation periods with respective entry and exit times, the USB host controller or the USB client controller is able to start and end the one or more scheduled low-power operation periods without incurring additional signaling, thus improving efficiency of the USB low-power operation. Further, by communicating the low-power operation schedule using USB standard packets, it is possible to preserve compatibility with USB standards.