公开(公告)号：US07319053B2

公开(公告)日：2008-01-15

申请号：US11355214

申请日：2006-02-14

Applicant: Vivek Subramanian ,  James M. Cleeves

Inventor： Vivek Subramanian ,  James M. Cleeves

IPC: H01L21/82

CPC classification number: G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract translation: 公开了一种非常高密度的现场可编程存储器。 阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

公开(公告)号：US07160761B2

公开(公告)日：2007-01-09

申请号：US10251206

申请日：2002-09-19

Applicant: James M. Cleeves ,  Vivek Subramanian

Inventor： James M. Cleeves ,  Vivek Subramanian

IPC: H01L21/82

CPC classification number: G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

公开(公告)号：US07071565B2

公开(公告)日：2006-07-04

申请号：US10255884

申请日：2002-09-26

Applicant: Calvin K. Li ,  N. Johan Knall ,  Michael A. Vyvoda ,  James M. Cleeves ,  Vivek Subramanian

Inventor： Calvin K. Li ,  N. Johan Knall ,  Michael A. Vyvoda ,  James M. Cleeves ,  Vivek Subramanian

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  G11C8/00

CPC classification number: H01L27/0688 ,  H01L21/32135 ,  H01L21/8221 ,  H01L27/1214 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three dimensional circuit structure including tapered pillars between first and second signal lines. An apparatus including a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate; a second plurality of spaced apart coplanar conductors disposed in a second plane, the second plane parallel to and different from the first plane; and a plurality of cells disposed between one of the first conductors and one of the second conductors, wherein each of the plurality of cells have a re-entrant profile.

公开(公告)号：US20060134837A1

公开(公告)日：2006-06-22

申请号：US11354470

申请日：2006-02-14

Applicant: Vivek Subramanian ,  James Cleeves

Inventor： Vivek Subramanian ,  James Cleeves

IPC: H01L21/82

CPC classification number: G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

公开(公告)号：US20060025319A1

公开(公告)日：2006-02-02

申请号：US10902202

申请日：2004-07-29

Applicant: Vivek Subramanian ,  Pravin Shah ,  Kavssery Ananthapadmanabhan

Inventor： Vivek Subramanian ,  Pravin Shah ,  Kavssery Ananthapadmanabhan

IPC: A61K8/00

CPC classification number: A61K8/26 ,  A61Q19/10

Abstract: The present invention relates to personal wash compositions comprising, non-silicate particles, wherein the basal layer(s) carries a net cationic charge. The use of these specific particles results in enhanced properties (e.g., enhanced foaming, hydrotroping) of the personal wash products. The invention further discloses process for decreasing viscosity and/or increasing foam comprising formulating compositions with non-silicate layer compounds as specified.

Abstract translation: 本发明涉及包含非硅酸盐颗粒的个人洗涤组合物，其中基底层承载净阳离子电荷。 这些特定颗粒的使用导致个人洗涤产品的增强的性能（例如，增强的起泡，水解加工）。 本发明进一步公开了降低粘度和/或增加泡沫的方法，其中包括按照规定的非硅酸盐层化合物配制组合物。

公开(公告)号：US06515888B2

公开(公告)日：2003-02-04

申请号：US09928969

申请日：2001-08-13

Applicant: Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  P. Michael Farmwald ,  N. Johan Knall

Inventor： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  P. Michael Farmwald ,  N. Johan Knall

IPC: G11C1100

CPC classification number: H01L27/101 ,  G11C17/16 ,  H01L27/0688

Abstract: A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

Abstract translation: 低成本存储单元阵列包括多个垂直堆叠的存储单元层。 在一种形式中，每个存储单元的特征在于小的横截面积和小于6.3微安培的读取电流。 所得到的存储器阵列具有缓慢的访问时间，并且非常适合于数字媒体存储，其中访问时间要求低，并且与所公开的存储器阵列相关联的显着的成本降低特别有吸引力。 在另一种形式中，每个存储器单元包括反熔丝层和二极管部件，其中至少一个二极管部件被重掺杂（掺杂浓度大于1019 / cm3），并且其中读取电流大（高达500mA）。

公开(公告)号：US06413802B1

公开(公告)日：2002-07-02

申请号：US09695532

申请日：2000-10-23

Applicant: Chenming Hu ,  Tsu-Jae King ,  Vivek Subramanian ,  Leland Chang ,  Xuejue Huang ,  Yang-Kyu Choi ,  Jakub Tadeusz Kedzierski ,  Nick Lindert ,  Jeffrey Bokor ,  Wen-Chin Lee

Inventor： Chenming Hu ,  Tsu-Jae King ,  Vivek Subramanian ,  Leland Chang ,  Xuejue Huang ,  Yang-Kyu Choi ,  Jakub Tadeusz Kedzierski ,  Nick Lindert ,  Jeffrey Bokor ,  Wen-Chin Lee

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

Abstract translation: FinFET器件采用传统的平面MOSFET技术制造。 器件制造在覆盖绝缘层（例如SIMOX）的硅层中，器件从绝缘层延伸为翅片。 在通道的两侧设置双门，以提供增强的驱动电流，并有效抑制短路效应。 可以在源极和漏极之间提供多个通道以增加电流容量。 在一个实施例中，两个晶体管可以堆叠在鳍中以提供具有共享栅极的CMOS晶体管对。

公开(公告)号：US06385074B1

公开(公告)日：2002-05-07

申请号：US09748816

申请日：2000-12-22

Applicant: Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

Inventor： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

IPC: G11C1700

CPC classification number: H01L27/1021 ,  G11C11/5692 ,  G11C17/14 ,  G11C17/16 ,  G11C2213/71 ,  H01L27/0203 ,  H01L27/115

Abstract: An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.

Abstract translation: 集成电路器件包括三维存储器阵列和阵列端子电路，用于向阵列的选定存储单元提供不同于读取电压的写入电压。 两个电压都不一定等于提供给集成电路的VDD电源电压。 特别是如果大于VDD的写入电压可以由片上电压发生器（例如电荷泵）产生，其可能需要不期望的大量管芯面积，特别是相对于较高位密度的三维存储器阵列 完全以半导体衬底上的层形成。 在几个优选实施例中，存储器阵列正下方的区域有利地用于布置写入电压发生器中的至少一些，从而在写入操作期间将发生器定位在选定的存储器单元附近。

公开(公告)号：US06351406B1

公开(公告)日：2002-02-26

申请号：US09714440

申请日：2000-11-15

Applicant: Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  P. Michael Farmwald ,  James M. Cleeves

Inventor： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  P. Michael Farmwald ,  James M. Cleeves

IPC: G11C1700

CPC classification number: G11C17/14 ,  G11C11/5692 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/76

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract translation: 公开了一种非常高密度的现场可编程存储器。 阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

公开(公告)号：US20160219516A1

公开(公告)日：2016-07-28

申请号：US14607048

申请日：2015-01-27

Applicant: Vivek Subramanian ,  Elad Alon ,  Vikram Pavate

Inventor： Vivek Subramanian ,  Elad Alon ,  Vikram Pavate

IPC: H04W52/02 ,  H04L5/14 ,  H04L12/44

CPC classification number: H04W52/0219 ,  H04L12/44 ,  H04L2012/445 ,  Y02D70/00 ,  Y02D70/1224 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/162 ,  Y02D70/164 ,  Y02D70/22

Abstract: Systems and methods for implementing power management features while providing a wireless asymmetric network are disclosed herein. In one embodiment, a system includes a hub having a wireless control device that is configured to control communications and power consumption in the wireless asymmetric network architecture and sensor nodes each having at least one sensor and a wireless device with a transmitter and a receiver to enable bi-directional communications with the wireless control device of the hub. The wireless control device is configured to determine a scheduled timing of operating each sensor node during a first time period that is close in time with respect to a transmit window of the transmitter and during a second time period that is close in time with respect to a receive window of the receiver for each wireless device to reduce power consumption of the wireless devices of the sensor nodes.

Abstract translation: 本文公开了在提供无线非对称网络的同时实现电力管理特征的系统和方法。 在一个实施例中，系统包括具有无线控制设备的集线器，无线控制设备被配置为控制无线非对称网络架构中的通信和功耗，每个传感器节点具有至少一个传感器和具有发射机和接收机的无线设备，以使能 与集线器的无线控制设备的双向通信。 无线控制设备被配置为确定在相对于发射机的发射窗口在时间上接近的第一时间段期间以及在相对于发射机的时间接近的第二时间段期间操作每个传感器节点的调度定时 接收每个无线设备的接收窗口，以减少传感器节点的无线设备的功耗。