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    Direct digital access arrangement circuitry and method for connecting to phone lines
    41.
    发明授权
    Direct digital access arrangement circuitry and method for connecting to phone lines 失效
    用于连接到电话线的直接数字接入安排电路和方法

    公开(公告)号：US07463675B2

    公开(公告)日：2008-12-09

    申请号：US11398090

    申请日：2006-04-05

    申请人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

    发明人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

    IPC分类号： H04B1/38 ,  H04L5/16

    CPC分类号： H04M1/573 ,  H04L7/033 ,  H04L25/0266 ,  H04L25/06 ,  H04M1/76 ,  H04M3/007 ,  H04M11/06 ,  H04M19/001 ,  H04M19/02

    摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

    摘要翻译： 提供了一种适用于电话，医疗仪器，工业过程控制和其他应用的隔离系统。 本发明的优选实施例包括电容隔离屏障，通过数字信号传送数字信号。 该系统提供跨越隔离屏障的通信手段，其高度免疫幅度和相位噪声干扰。 可以在隔离屏障的一侧采用时钟恢复电路，从跨屏障通信的数字信号提取定时信息，并且滤除在屏障处引入的相位噪声的影响。 Δ-Σ转换器可以设置在隔离屏障的两侧以在模拟和数字域之间转换信号。 隔离电源也可以设置在屏障的隔离侧上，由此响应于穿过隔离屏障接收的数字数据产生直流电流。 最后，提供双向隔离系统，由此使用单对隔离电容器实现数字信号的双向通信。 在优选实施例中，跨屏障通信的数字数据由与其他数字控制，信令和成帧信息在时间上多路复用的数字delta-sigma数据信号组成。

    Ratiometric transmit path architecture for communication systems
    42.
    发明授权
    Ratiometric transmit path architecture for communication systems 有权
    通信系统的比例传输路径架构

    公开(公告)号：US07376396B2

    公开(公告)日：2008-05-20

    申请号：US11096133

    申请日：2005-03-31

    申请人： David R. Welland ,  Caiyi Wang

    发明人： David R. Welland ,  Caiyi Wang

    IPC分类号： H04B1/40 ,  H03C1/52

    CPC分类号： H04B1/403

    摘要： A ratiometric transmit path architecture for communication systems and related methods are disclosed. This ratiometric transmit path architecture utilizes a single local oscillator signal and dividers to provide mixing signals for intermediate frequency (IF) mixing circuitry and feedback mixing circuitry, thereby eliminating the need for separate IF and radio frequency (RF) voltage controlled oscillators (VCOs) in prior solutions.

    摘要翻译： 公开了用于通信系统和相关方法的比例传输路径架构。 这种比例传输路径架构利用单个本地振荡器信号和分频器来为中频（IF）混频电路和反馈混频电路提供混频信号，从而消除对单独的IF和射频（RF）压控振荡器（VCO）的需要 以前的解决方案。

    Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications
    43.
    发明授权
    Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications 有权
    用于操作用于合成用于无线通信的高频信号的PLL的方法和装置

    公开(公告)号：US07353011B2

    公开(公告)日：2008-04-01

    申请号：US11180267

    申请日：2005-07-13

    申请人： David R. Welland ,  Caiyi Wang

    发明人： David R. Welland ,  Caiyi Wang

    IPC分类号： H04B7/00 ,  H04B1/06

    CPC分类号： H03L7/193 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/199 ,  H03L7/23 ,  H03L2207/06

    摘要： A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

    摘要翻译： 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过首先从VCO输出时钟的分割版本产生多个相移信号来导出模拟控制信号。 第二，可以检测多个相移信号和参考时钟的分割版本之间的相位差，然后转换成模拟控制信号。

    Direct digital access arrangement circuitry and method for connecting to phone lines
    44.
    发明授权
    Direct digital access arrangement circuitry and method for connecting to phone lines 失效

    公开(公告)号：US07301995B2

    公开(公告)日：2007-11-27

    申请号：US10780219

    申请日：2004-02-17

    申请人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

    发明人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

    IPC分类号： H04B1/38 ,  H04L5/16

    CPC分类号： H04M1/573 ,  H04L7/033 ,  H04L25/0266 ,  H04L25/06 ,  H04M1/76 ,  H04M3/007 ,  H04M11/06 ,  H04M19/001 ,  H04M19/02

    摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

    Isolation system with digital communication across a capacitive barrier
    47.
    发明授权
    Isolation system with digital communication across a capacitive barrier 失效

    公开(公告)号：US07154940B2

    公开(公告)日：2006-12-26

    申请号：US10606231

    申请日：2003-06-25

    申请人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

    发明人： Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

    IPC分类号： H04B1/38

    CPC分类号： H04L25/0266 ,  H04L7/033 ,  H04L25/06 ,  H04M11/06

    摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

    Method and apparatus for generating a variable capacitance for synthesizing high-frequency signals for wireless communications
    50.
    发明授权
    Method and apparatus for generating a variable capacitance for synthesizing high-frequency signals for wireless communications 有权
    用于高频信号和相关方法的可控振荡器电路

    公开(公告)号：US06760575B2

    公开(公告)日：2004-07-06

    申请号：US09973634

    申请日：2001-10-09

    申请人： David R. Welland

    发明人： David R. Welland

    IPC分类号： H04B106

    CPC分类号： H03L7/099 ,  H03B21/02 ,  H03J2200/10 ,  H03L7/10

    摘要： A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. The continuously variable capacitance may be formed by using a plurality of separate capacitance circuits. The individual capacitance circuits may include two capacitors coupled to a variable resistance element. The variable resistance element may be a transistor controlled by an analog control voltage. The total capacitance of the continuously variable capacitance may be substantially linear with respect to the phase of the VCO output while the individual capacitance circuits exhibit nonlinear behavior.

    摘要翻译： 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 可以通过使用多个单独的电容电路来形成连续可变电容。 各个电容电路可以包括耦合到可变电阻元件的两个电容器。 可变电阻元件可以是由模拟控制电压控制的晶体管。 连续可变电容的总电容可以相对于VCO输出的相位基本上是线性的，而各个电容电路表现出非线性行为。