公开(公告)号：US5903751A

公开(公告)日：1999-05-11

申请号：US931807

申请日：1997-09-16

申请人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

发明人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30054

摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

摘要翻译： 公开了一种使用计算机指令流预测分支指令的计算机处理器中的分支目标缓冲器电路。 分支目标缓冲器电路使用分支目标缓冲器高速缓存，其存储关于先前执行的分支指令的分支信息。 存储在分支目标缓冲区高速缓存中的分支信息由每个分支指令的最后一个字节寻址。 当计算机处理器中的指令获取单元获取指令块时，它向分支目标缓冲器电路发送指令指针。 基于指令指针，分支目标缓冲器电路查找分支目标缓冲区高速缓存以查看正在获取的块中的任何指令是否是分支指令。 当分支目标缓冲器电路在分支目标缓冲器高速缓存中找到即将到来的分支指令时，分支目标缓冲器电路通知指令获取单元关于即将到来的分支指令。

公开(公告)号：US5586278A

公开(公告)日：1996-12-17

申请号：US639244

申请日：1996-04-22

申请人： David B. Papworth ,  Glenn J. Hinton

发明人： David B. Papworth ,  Glenn J. Hinton

IPC分类号： G06F9/38

CPC分类号： G06F9/3863

摘要： A method of state recovery following a branch misprediction or an undetected branch instruction. If, during execution of a branch instruction in an out-of-order unit, it is determined that the branch has been mispredicted, or if a taken branch has not been detected, then a JEClear signal is asserted to flush the instruction fetch unit and decoder section, and to change the instruction pointer to the actual target address. Within the out-of-order section, the instructions preceding the branch instruction are allowed to continue execution and proceed to in-order retirement. Simultaneously, instructions fetched at the actual target address are decoded, but not allowed to issue therefrom until the branch instruction has been retired from the out-of-order section, after which all instructions within the out-of-order section are flushed, and then decoded instructions are allowed to issue from the decoder. The state recovery method advantageously provides efficient utilization of processor time.

摘要翻译： 分支错误预测或未检测到的分支指令之后的状态恢复方法。 如果在执行无序单元中的分支指令时，确定分支已经被错误预测，或者如果未被检测到被采取的分支，则断言JEClear信号以刷新指令获取单元，并且 解码器部分，并将指令指针更改为实际目标地址。 在无序部分中，分支指令之前的指令被允许继续执行，并进行到订单退休。 同时，在实际目标地址处获取的指令被解码，但是在分支指令已经从无序部分退出之前不允许发出指令，之后清除无序部分内的所有指令，以及 则解码指令被允许从解码器发出。 状态恢复方法有利地提供了处理器时间的有效利用。

公开(公告)号：US5812839A

公开(公告)日：1998-09-22

申请号：US851141

申请日：1997-05-05

申请人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

发明人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/3844 ,  G06F9/3863 ,  G06F9/3885

摘要： A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.

摘要翻译： 公开了一种用于流水线处理器的四级分支指令解析系统。 分支指令解析系统的第一阶段预测指令流内分支指令的存在和结果，使得指令获取单元可以连续地获取指令。 第二阶段解码所有提取的指令。 如果解码级确定由第一级预测的分支指令不是分支指令，则解码级别刷新流水线并以校正的地址重新启动处理器。 解码阶段验证分支预测阶段所做的所有分支预测。 最后，解码阶段对分支预测阶段未预测的分支进行分支预测。 第三阶段执行所有分支指令以确定最终分支结果和最终分支目标地址。 分支执行阶段将最终分支结果和最终分支目标地址与预测的分支结果和预测分支目标地址进行比较，以确定处理器是否必须冲洗微处理器流水线的前端并以修正的地址重新启动。 最终的分支解决阶段退出所有分支指令。 退休阶段确保在错误预测的分支之后提取的任何指令不会被永久保留。

公开(公告)号：US5604753A

公开(公告)日：1997-02-18

申请号：US177861

申请日：1994-01-04

申请人： John M. Bauer ,  Glenn J. Hinton ,  Gregory P. Meece ,  David B. Papworth

发明人： John M. Bauer ,  Glenn J. Hinton ,  Gregory P. Meece ,  David B. Papworth

IPC分类号： G06F11/10

CPC分类号： G06F11/1064

摘要： A method and apparatus for performing error correction on data from an external memory is described. The present invention includes a method and apparatus for receiving data from an external memory source and determining if the data has an error. The data is forwarded to the requesting unit while the error correction is performed on the data, such that the two operations are performed in parallel.The present invention also includes a method and apparatus for subsequently correcting data if a single bit error exists. The corrected data is then forwarded to the requesting unit during the next cycle. Also if an error is detected, the present invention produces an indication to the device. The device is flushed in response to the indication.

摘要翻译： 描述用于对来自外部存储器的数据执行纠错的方法和装置。 本发明包括用于从外部存储器源接收数据并确定数据是否具有错误的方法和装置。 在对数据执行错误校正的同时将数据转发到请求单元，使得并行执行两个操作。 本发明还包括如果存在单个位错误则用于随后校正数据的方法和装置。 然后在下一个周期中将修正的数据转发到请求单元。 此外，如果检测到错误，则本发明产生对该装置的指示。 响应于指示，将设备刷新。

公开(公告)号：US06349380B1

公开(公告)日：2002-02-19

申请号：US09267796

申请日：1999-03-12

申请人： Shahrokh Shahidzadeh ,  Bryant E. Bigbee ,  David B. Papworth ,  Frank Binns ,  Robert P. Colwell

发明人： Shahrokh Shahidzadeh ,  Bryant E. Bigbee ,  David B. Papworth ,  Frank Binns ,  Robert P. Colwell

IPC分类号： G06F9355

CPC分类号： G06F9/342 ,  G06F12/0292

摘要： A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

摘要翻译： 用于提供超过32位的扩展线性地址的微处理器。 可以通过将线性地址与段选择器扩展连接，或者通过连接来自两个寄存器的值来提供扩展线性地址。 执行线性地址到物理地址的分级转换，其中层级中的层数取决于线性地址是否是扩展线性地址。

公开(公告)号：US5307506A

公开(公告)日：1994-04-26

申请号：US945571

申请日：1992-09-16

申请人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

发明人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

IPC分类号： G06F13/40

CPC分类号： G06F13/4022

摘要： A parallel processor has a plurality of communication buses advantageously interconnecting the arithmetic processor elements, the memory controller elements, a global controller circuitry, and input/output processors. The processor preferably has at least one central processing unit cluster, the cluster having at least one integer processor and one floating point processor. A plurality of I/F buses interconnect the integer and floating point processors of a cluster for communications therebetween. Integer load buses connect the integer processors of each cluster and selectively connect those processors to the memory controllers for transferring data from memory to the clusters and for providing inter-integer processor data communications. A plurality of floating point load buses connect the floating point processors of the clusters to selected memory controllers for transferring data from the controllers to the floating point processors and for providing inter-floating point processor data communications. A plurality of physical address buses provide one-way communications for transferring memory addresses from the integer processors to the memories and a plurality of storage buses connect the floating point processors to the memory controllers along a one-way communications path for transferring data to be stored in the memories. The hardware architecture provides advantageous communications between the elements of the data processing system for enabling wide bandwidth communications and high instruction throughput.

摘要翻译： 并行处理器具有多个通信总线，其有利地将算术处理器元件，存储器控制器元件，全局控制器电路和输入/输出处理器互连。 处理器优选地具有至少一个中央处理单元簇，该簇具有至少一个整数处理器和一个浮点处理器。 多个I / F总线互连簇的整数和浮点处理器，用于在其间进行通信。 整数负载总线连接每个集群的整数处理器，并将这些处理器选择性地连接到存储器控制器，以将数据从存储器传输到集群，并提供整数处理器数据通信。 多个浮点负载总线将集群的浮点处理器连接到选择的存储器控​​制器，用于将数据从控制器传送到浮点处理器，并提供浮点间处理器数据通信。 多个物理地址总线提供用于将存储器地址从整数处理器传送到存储器的单向通信，并且多个存储总线沿着单向通信路径将浮点处理器连接到存储器控制器，用于传送要存储的数据 在回忆中 硬件架构提供数据处理系统的元件之间的有利通信，以实现宽带宽通信和高指令吞吐量。

公开(公告)号：US5057837A

公开(公告)日：1991-10-15

申请号：US476108

申请日：1990-01-30

申请人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

发明人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F9/30149 ,  G06F12/0844 ,  G06F12/0875 ,  G06F9/30025 ,  G06F9/30178 ,  G06F9/321 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3891

摘要： A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

摘要翻译： 一种用于将压缩形式的指令字存储在存储介质上的方法和装置，所述指令字具有多个指令字段，与每个指令字相关联的特征，具有至少等于 指令字中的指令字段。 每个指令字段与掩码字的位相关联，因此使用掩码字，只有非零指令字段需要存储在存储器中。 指令压缩方法有利地用在高速缓存未命中引擎中，用于在发生高速缓存未命中之后重新填充指令高速缓存的部分。

公开(公告)号：US5179680A

公开(公告)日：1993-01-12

申请号：US707917

申请日：1991-05-30

申请人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

发明人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3891 ,  G06F12/0844 ,  G06F12/0875 ,  G06F9/30025 ,  G06F9/3017 ,  G06F9/30178 ,  G06F9/321 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3885

摘要： A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

摘要翻译： 一种用于将压缩形式的指令字存储在存储介质上的方法和装置，所述指令字具有多个指令字段，与每个指令字相关联的特征，具有至少等于 指令字中的指令字段。 每个指令字段与掩码字的位相关联，因此使用掩码字，只有非零指令字段需要存储在存储器中。 指令压缩方法有利地用在高速缓存未命中引擎中，用于在发生高速缓存未命中之后重新填充指令高速缓存的部分。

公开(公告)号：US4920477A

公开(公告)日：1990-04-24

申请号：US40990

申请日：1987-04-20

申请人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

发明人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

IPC分类号： G06F11/14 ,  G06F12/10

CPC分类号： G06F12/1063 ,  G06F11/1407

摘要： A data processor has a central processing unit and at least one pipelined memory controller circuitry. The central processing unit addresses data in the memory using a virtual address memory table lookaside buffer and features a data miss recovery circuitry wherein, after a memory access error condition has been detected, the instruction causing the error condition, and those instructions entering the memory pipeline after the instruction causing the error condition, are replayed. The method and apparatus for replaying the instructions use first in-first out buffers for storing the virtual address data and instruction status data relating to each memory access instruction. That stored data is then retrieved after an error condition is detected so that the instruction sequence, beginning at the data miss, can be replayed.

摘要翻译： 数据处理器具有中央处理单元和至少一个流水线存储器控制器电路。 中央处理单元使用虚拟地址存储器表后置缓冲器来对存储器中的数据进行寻址，并具有数据未命中恢复电路，其中在检测到存储器访问错误状况之后，引起错误状态的指令，以及进入存储器管线的指令 导致错误状态的指令后，重播。 用于重放指令的方法和装置使用先进先出的缓冲器来存储与每个存储器访问指令相关的虚拟地址数据和指令状态数据。 然后在检测到错误条件之后检索存储的数据，使得可以重放从数据未命中开始的指令序列。

公开(公告)号：US4833599A

公开(公告)日：1989-05-23

申请号：US41081

申请日：1987-04-20

申请人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

发明人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

IPC分类号： G06F9/26 ,  G06F9/28 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30094 ,  G06F9/264 ,  G06F9/28 ,  G06F9/30061 ,  G06F9/3842 ,  G06F9/3885

摘要： In a parallel data processing system having a plurality of separately operating arithmetic processing units, a method and apparatus allows a plurality of branch instructions to be operated upon in a single machine cycle. The branch instructions have associated therewith a hierarchical priority system and the method and apparatus determine which branch, if any, should be taken. In particular, the method and apparatus simultaneously determine, during the parallel execution of the branch instructions, whether any branch test condition associated with a branch instruction is true, and independently, the target address for each branch instruction and a fall-through instruction address if a branch instruction is not taken.

摘要翻译： 在具有多个单独操作的算术处理单元的并行数据处理系统中，一种方法和装置允许在单个机器周期中操作多个分支指令。 分支指令已经与分层优先级系统相关联，并且该方法和装置确定应该采用哪个分支（如果有的话）。 特别地，该方法和装置在并行执行分支指令期间同时确定与分支指令相关联的任何分支测试条件是否为真，并且独立地确定每个分支指令的目标地址和下降指令地址if 不执行分支指令。