公开(公告)号：US10373697B1

公开(公告)日：2019-08-06

申请号：US15897550

申请日：2018-02-15

Applicant: SanDisk Technologies LLC

Inventor： Chun-Hung Lai ,  Rajdeep Gautam ,  Ching-Huang Lu ,  Shih-Chung Lee

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/16 ,  G11C16/04 ,  G11C11/56 ,  G11C7/14

CPC classification number: G11C16/3445 ,  G11C7/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.

公开(公告)号：US10204689B1

公开(公告)日：2019-02-12

申请号：US15699513

申请日：2017-09-08

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Anubhav Khandelwal ,  Changyuan Chen ,  Cynthia Hsu ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C11/56

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

公开(公告)号：US10068651B1

公开(公告)日：2018-09-04

申请号：US15621215

申请日：2017-06-13

Applicant: SanDisk Technologies LLC

Inventor： Vinh Diep ,  Wei Zhao ,  Ashish Baraskar ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/14 ,  G11C16/24 ,  G11C16/04

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation. A pre-charge operation occurs in which a channel voltage is increased to a positive level. This reduces a channel gradient which can lead to a disturb of the select gate transistors. One approach involves applying a voltage at an intermediate level to the source and/or drain ends of the memory strings, before increasing the voltage from the intermediate level to a peak erase level. Another approach involves driving the word line voltages at a negative level and then at a higher level to down couple and then up couple the channel voltages. The techniques may be adjusted depending on whether the word lines are at a positive floating voltage at a start of the erase operation, and based on a level of the floating voltage.

公开(公告)号：US11037640B2

公开(公告)日：2021-06-15

申请号：US16900015

申请日：2020-06-12

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Ching-Huang Lu ,  Vinh Diep ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C11/56

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

公开(公告)号：US10811109B2

公开(公告)日：2020-10-20

申请号：US16233723

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Ching-Huang Lu ,  Vinh Diep ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C11/56

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

公开(公告)号：US10804282B2

公开(公告)日：2020-10-13

申请号：US16272468

申请日：2019-02-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Fei Zhou ,  Ching-Huang Lu ,  Raghuveer S. Makala

IPC: H01L27/11558 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11556

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and memory stack structures are formed through the alternating stack. A backside trench is formed through the alternating stack, and backside recesses are formed by removing the sacrificial material layers. An undoped aluminum oxide backside blocking dielectric layer is formed in the backside recesses and on sidewalls the backside trench. A portion of the undoped aluminum oxide backside blocking dielectric layer located at an upper end of the backside trench is converted into a carbon-doped aluminum oxide layer. An electrically conductive material is deposited in the backside recesses and at peripheral regions of the backside trench. The electrically conductive material at the peripheral regions of the backside trench is removed by an etch process, with the carbon-doped aluminum oxide layer providing etch resistivity during the etch process.

公开(公告)号：US20200312414A1

公开(公告)日：2020-10-01

申请号：US16900015

申请日：2020-06-12

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Ching-Huang Lu ,  Vinh Diep ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/24 ,  G11C16/10 ,  G11C11/56

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

公开(公告)号：US10685978B1

公开(公告)日：2020-06-16

申请号：US16267592

申请日：2019-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ching-Huang Lu ,  Wei Zhao ,  Yanli Zhang ,  James Kai

IPC: H01L29/792 ,  H01L21/00 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: Electrical isolation between adjacent stripes of drain-select-level electrically conductive layers can be provided by forming a drain-select-level isolation structure between neighboring rows of memory stack structures. The drain-select-level isolation structure can partially cut through upper regions of the neighboring rows of memory stack structures. Vertical semiconductor channels of the neighboring rows of memory stack structures include a lower tubular segment and an upper semi-tubular segment that contact the drain-select-level isolation structure. Electrical current through drain select levels is limited to the semi-tubular segment of each vertical semiconductor channel. Alternatively, the drain-select-level isolation structure can be formed around the memory stack structures within the neighboring rows of memory stack structures. Ion implantation can be used to suppress conduction of electrical current through portions of vertical semiconductor channels that are proximal to the drain-select-level isolation structure.

公开(公告)号：US10665313B1

公开(公告)日：2020-05-26

申请号：US16402151

申请日：2019-05-02

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Henry Chin ,  Jian Chen

IPC: G11C29/00 ,  G11C29/02 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  G11C29/38 ,  G11C16/34 ,  G11C29/12

Abstract: Techniques are described for detecting a short circuit between a word line and a source line in a memory device, and to a method for recovering from such a short circuit. In one aspect, the short circuit is detected in a program operation when a selected word line completes programming after an unusually low number of program loops. A further check is performed to confirm that there is a short circuit. The short circuited word line is then erased and a recovery read is performed for previously-programmed word lines. In another aspect, a short circuit is detected in a read operation.

公开(公告)号：US10665301B1

公开(公告)日：2020-05-26

申请号：US16245491

申请日：2019-01-11

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C11/56 ,  G11C16/26

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.