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    PROGRAMMING PROCESS COMBINING ADAPTIVE VERIFY WITH NORMAL AND SLOW PROGRAMMING SPEEDS IN A MEMORY DEVICE
    41.
    发明申请
    PROGRAMMING PROCESS COMBINING ADAPTIVE VERIFY WITH NORMAL AND SLOW PROGRAMMING SPEEDS IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20200303025A1

    公开(公告)日：2020-09-24

    申请号：US16893626

    申请日：2020-06-05

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

    IPC: G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

    Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

    MEMORY DEVICE WITH CONNECTED WORD LINES FOR FAST PROGRAMMING
    43.
    发明申请
    MEMORY DEVICE WITH CONNECTED WORD LINES FOR FAST PROGRAMMING 审中-公开

    公开(公告)号：US20190371406A1

    公开(公告)日：2019-12-05

    申请号：US16000237

    申请日：2018-06-05

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

    IPC: G11C16/08 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  H01L27/1157

    Abstract: Apparatuses and techniques for fast programming and read operations for memory cells. A group of word lines comprising a selected word line and one or more adjacent word lines are driven with a common voltage signal during program and read operations. The word lines may be permanently connected to one another or connected by a switch. In another approach, the word lines are driven separately by common voltage signals. In a set of blocks, one block of memory cells can be provided with connected word lines to provide a relatively high access speed, while another block of memory cells has disconnected word lines to provide a higher storage density. In another aspect, the memory cells of a word line are divided into portions, and a portion which is closest to a row decoder is reserved for high access speed with a low storage density.

    SINGLE PULSE VERIFICATION OF MEMORY CELLS
    44.
    发明申请
    SINGLE PULSE VERIFICATION OF MEMORY CELLS 审中-公开

    公开(公告)号：US20190252030A1

    公开(公告)日：2019-08-15

    申请号：US15963647

    申请日：2018-04-26

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Jianzhi Wu ,  Gerrit Jan Hemink

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24

    Abstract: Disclosed herein is related to a memory device and a method of verifying a programmed status of the memory device. The memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.

    Smart erase scheme
    48.
    发明授权
    Smart erase scheme 有权

    公开(公告)号：US11355198B1

    公开(公告)日：2022-06-07

    申请号：US17152435

    申请日：2021-01-19

    Applicant: SanDisk Technologies LLC

    Inventor： Fanqi Wu ,  Huai-Yuan Tseng ,  Sarath Puthenthermadam

    IPC: G11C16/34 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11556

    Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase voltage pulse to a set of non-volatile storage elements; determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements; and applying, in a second erase loop of the plurality of erase loops, the second erase voltage pulse to the set of non-volatile storage elements.

    Systems and methods for program verification on a memory system
    50.
    发明授权
    Systems and methods for program verification on a memory system 有权

    公开(公告)号：US11244735B2

    公开(公告)日：2022-02-08

    申请号：US16793749

    申请日：2020-02-18

    Applicant: SanDisk Technologies LLC

    Inventor： Zhiping Zhang ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

    IPC: G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C16/26

    Abstract: A method for memory program verification includes performing a write operation on memory cells of a memory device. The method also includes identifying memory strings associated with respective memory cells of the memory cells. The method also includes identifying a first memory string of the memory strings. The method also includes disabling a portion of a write verification for the first memory string. The method also includes enabling the portion of the write verification for other memory strings of the memory strings. The method also includes performing at least the portion of the write verification operation on write verification enabled memory strings.

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