公开(公告)号：US20210134819A1

公开(公告)日：2021-05-06

申请号：US16671025

申请日：2019-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Johann Alsmeier ,  Teruo Okina

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11575 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

Abstract: A method of forming a device structure includes forming a memory-level structure including a three-dimensional memory device over a front side surface of a semiconductor substrate, forming memory-side dielectric material layers over the memory-level structure, bonding a handle substrate to the memory-side dielectric material layers, thinning the semiconductor substrate while the handle substrate is attached to the memory-side dielectric material layers, forming a driver circuit including field effect transistors on a backside semiconductor surface of the semiconductor substrate after thinning the semiconductor substrate, and removing the handle substrate from the memory-side dielectric material layers.

公开(公告)号：US20210050372A1

公开(公告)日：2021-02-18

申请号：US16743436

申请日：2020-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Seung-Yeul YANG ,  Fei ZHOU

IPC: H01L27/11597 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A ferroelectric memory device includes a semiconductor channel, a gate electrode, and a ferroelectric memory element located between the semiconductor channel and the gate electrode. The ferroelectric memory element includes at least one ferroelectric material portion and at least one antiferroelectric material portion.

公开(公告)号：US20170148811A1

公开(公告)日：2017-05-25

申请号：US15354116

申请日：2016-11-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tong ZHANG ,  Johann ALSMEIER ,  James KAI ,  Jin LIU ,  Yanli ZHANG

IPC: H01L27/115 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L28/00

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.

公开(公告)号：US20170098655A1

公开(公告)日：2017-04-06

申请号：US15379927

申请日：2016-12-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiying COSTA ,  Dana LEE ,  Yanli ZHANG ,  Johann ALSMEIER ,  Yingda DONG ,  Akira MATSUDAIRA

IPC: H01L27/11524 ,  H01L29/788 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/792 ,  H01L27/11556

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7883 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.