公开(公告)号：US09496283B1

公开(公告)日：2016-11-15

申请号：US14821845

申请日：2015-08-10

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L27/00 ,  H01L27/12 ,  H01L29/417 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/845 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

Abstract: A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

Abstract translation: 晶体管包括由衬底支撑并具有源极区，沟道区和漏极区的有源区。 栅极堆叠在沟道区域上方延伸，并且第一侧壁围绕栅极堆叠。 分别在与第一侧壁相邻的有源区域的源极和漏极区域之上提供凸起的源极区域和凸起的漏极区域。 第二侧壁周向地围绕凸起的源极区域和升高的漏极区域中的每一个。 第二侧壁延伸在凸起源区域的顶表面上方，并且凸起的漏极区域限定由第一和第二侧壁横向限定的区域。 导电材料填充区域以分别形成源极接触和漏极接触到升高的源极区域和升高的漏极区域。

公开(公告)号：US09490355B2

公开(公告)日：2016-11-08

申请号：US14945936

申请日：2015-11-19

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  John Hongguang Zhang

IPC: H01L29/772 ,  H01L29/66 ,  H01L27/02 ,  H01L29/16 ,  H01L29/08 ,  H01L21/04 ,  H01L21/308 ,  H01L27/146 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/7722 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/308 ,  H01L27/0225 ,  H01L27/14679 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66416

Abstract: A static induction transistor is formed on a silicon carbide substrate doped with a first conductivity type. First recessed regions in a top surface of the silicon carbide substrate are filled with epitaxially grown gate regions in situ doped with a second conductivity type. Epitaxially grown channel regions in situ doped with the first conductivity type are positioned between adjacent epitaxial gate regions. Epitaxially grown source regions in situ doped with the first conductivity type are positioned on the epitaxial channel regions. The bottom surface of the silicon carbide substrate includes second recessed regions vertically aligned with the channel regions and silicided to support formation of the drain contact. The top surfaces of the source regions are silicided to support formation of the source contact. A gate lead is epitaxially grown and electrically coupled to the gate regions, with the gate lead silicided to support formation of the gate contact.

公开(公告)号：US20160307964A1

公开(公告)日：2016-10-20

申请号：US14960595

申请日：2015-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

Abstract translation: 在支撑衬底上形成电阻随机存取存储器（RRAM）结构，并且包括第一电极和第二电极。 第一电极由支撑衬底上的硅化物翅片和覆盖硅化物翅片的第一金属衬垫层制成。 具有可配置电阻性能的电介质材料层覆盖第一金属衬垫的至少一部分。 第二电极由覆盖电介质材料层的第二金属衬垫层和与第二金属衬垫层接触的金属填充物制成。 非易失性存储单元包括电连接在存取晶体管和位线之间的RRAM结构。

公开(公告)号：US09224845B1

公开(公告)日：2015-12-29

申请号：US14538877

申请日：2014-11-12

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang ,  Pierre Morin

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/772 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L21/04 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L29/7722 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/308 ,  H01L27/0225 ,  H01L27/14679 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66416

Abstract: A static induction transistor is formed on a silicon carbide substrate doped with a first conductivity type. First recessed regions in a top surface of the silicon carbide substrate are filled with epitaxially grown gate regions in situ doped with a second conductivity type. Epitaxially grown channel regions in situ doped with the first conductivity type are positioned between adjacent epitaxial gate regions. Epitaxially grown source regions in situ doped with the first conductivity type are positioned on the epitaxial channel regions. The bottom surface of the silicon carbide substrate includes second recessed regions vertically aligned with the channel regions and silicided to support formation of the drain contact. The top surfaces of the source regions are silicided to support formation of the source contact. A gate lead is epitaxially grown and electrically coupled to the gate regions, with the gate lead silicided to support formation of the gate contact.

Abstract translation: 在掺杂有第一导电类型的碳化硅衬底上形成静电感应晶体管。 在碳化硅衬底的顶表面中的第一凹陷区域填充有原位掺杂有第二导电类型的外延生长栅极区域。 原位掺杂有第一导电类型的外延生长沟道区位于相邻的外延栅区之间。 原位掺杂有第一导电类型的外延生长的源极区位于外延沟道区上。 碳化硅衬底的底表面包括与沟道区垂直对准的第二凹陷区域并硅​​化以支持漏极接触的形成。 源区的顶表面被硅化以支持源接触的形成。 栅极引线外延生长并电耦合到栅极区域，栅极引线硅化以支持栅极接触的形成。

公开(公告)号：US20150323739A1

公开(公告)日：2015-11-12

申请号：US14802504

申请日：2015-07-17

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: G02B6/132 ,  G02B6/136

CPC classification number: G02B6/43 ,  G02B6/122 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B6/4214 ,  G02B2006/12102

Abstract: A photonic integrated circuit includes optical circuitry fabricated over an underlying circuitry layer. The optical circuitry includes a dielectric material having recesses disposed within, layers of a light waveguide material deposited within the recesses, and lenses disposed over each layer of waveguide material. The underlying circuitry layer may include, for example, a semiconductor wafer as well as circuitry fabricated during front end of line (FEOL) semiconductor manufacturing such as, for example, sources, gates, drains, interconnects, contacts, resistors, and other circuitry that may be manufactured during FEOL processes. The underlying circuitry layer may also include circuitry manufactured during back end of line semiconductor manufacturing processes such as, for example, interconnect structures, metallization layers, and contacts.

Abstract translation: 光子集成电路包括在底层电路层上制造的光电路。 光学电路包括具有设置在沉积在凹部内的光波导材料的层内的凹槽的介电材料和设置在每层波导材料上的透镜。 底层电路层可以包括例如半导体晶片以及在前端（FEOL）半导体制造期间制造的电路，例如源，栅极，漏极，互连，触点，电阻器和其他电路，其中 可以在FEOL过程中制造。 底层电路层还可以包括在线半导体制造工艺的后端制造的电路，例如互连结构，金属化层和触点。