公开(公告)号：US08956942B2

公开(公告)日：2015-02-17

申请号：US13725528

申请日：2012-12-21

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7848

Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel (fin) and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed, thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.

Abstract translation: 通过在器件的制造期间在半导体沟道（鳍）和衬底之间插入绝缘层来防止FinFET器件中的沟道到衬底泄漏。 类似地，通过在源极/漏极区域和衬底之间插入绝缘层来隔离源极/漏极区域来防止FinFET器件中的源极/漏极到衬底泄漏。 形成这样的绝缘层将物理和电气上的导电路径与衬底隔离，从而防止电流泄漏。 在由多层堆叠构成的半导体鳍阵列中，去除底部材料，从而产生悬浮在硅表面上方的翅片阵列。 然后在剩余的顶部翅片材料下面形成的间隙填充氧化物以更好地支撑翅片并且将翅片阵列与基底隔离开。

公开(公告)号：US20140353717A1

公开(公告)日：2014-12-04

申请号：US13907411

申请日：2013-05-31

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare ,  Stephane Allegret-Maret ,  Bruce Doris ,  Kangguo Cheng

IPC: H01L29/786 ,  H01L27/092 ,  H01L27/11 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.

Abstract translation: 一种具有沟道外延硅的改进晶体管。 在一个方面，一种制造方法包括：在设置在衬底上的外延硅区域上形成栅极叠层结构，外延硅区域的宽度尺寸接近栅叠层结构的宽度尺寸; 以及从衬底生长升高的外延源和漏极，所述升高的外延源极和漏极与外延硅区域和栅极堆叠结构接触。 对于SRAM器件，进一步：去除与硅衬底和升高的源极和漏极接触的外延层，并且外延硅区域耦合到外延层，留下硅衬底上方的空间，并且在升高的外延源极和漏极之下; 并用绝缘层填充该空间，并将该凸起的外延源极和漏极以及晶体管的沟道与硅衬底隔离。

公开(公告)号：US20140175554A1

公开(公告)日：2014-06-26

申请号：US13725528

申请日：2012-12-21

Applicant: STMICROELECTRONICS , INC.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L27/088 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7848

Abstract: Channel-to-substrate leakage in a FinFET device can be prevented by inserting an insulating layer between the semiconducting channel (fin) and the substrate. Similarly, source/drain-to-substrate leakage in a FinFET device can be prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. The insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. If an array of semiconducting fins is made up of a multi-layer stack, the bottom material can be removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material can then be filled in with oxide to better support the fins and to isolate the array of fins from the substrate. The resulting FinFET device is fully substrate-isolated in both the gate region and the source/drain regions.

Abstract translation: 通过在半导体沟道（鳍）和衬底之间插入绝缘层，可以防止FinFET器件中的沟道对衬底的泄漏。 类似地，通过在源极/漏极区域和衬底之间插入绝缘层，可以防止FinFET器件中的源极/漏极到衬底的泄漏。 绝缘层在物理和电气上隔离了衬底的导电路径，从而防止电流泄漏。 如果半导体翅片的阵列由多层堆叠构成，则可以去除底部材料，从而产生悬浮在硅表面上方的翅片阵列。 然后可以用氧化物填充剩下的顶部翅片材料之下的产生的间隙，以更好地支撑翅片并将翅片阵列与基底隔离开。 所得到的FinFET器件在栅极区域和源极/漏极区域中完全衬底隔离。

公开(公告)号：US10134899B2

公开(公告)日：2018-11-20

申请号：US14983070

申请日：2015-12-29

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/161

Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

公开(公告)号：US10062690B2

公开(公告)日：2018-08-28

申请号：US15209662

申请日：2016-07-13

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC: H01L29/76 ,  H01L21/336 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L21/225 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US09905662B2

公开(公告)日：2018-02-27

申请号：US14976781

申请日：2015-12-21

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L29/41791 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.

公开(公告)号：US09847260B2

公开(公告)日：2017-12-19

申请号：US14969393

申请日：2015-12-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/823807 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

公开(公告)号：US09673222B2

公开(公告)日：2017-06-06

申请号：US15156506

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Kangguo Cheng ,  Bruce Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Rama Divakaruni

IPC: H01L27/12 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/84 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

公开(公告)号：US09520393B2

公开(公告)日：2016-12-13

申请号：US14587872

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L27/01 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/16 ,  H01L29/49

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7848

Abstract: Channel-to-substrate leakage in a FinFET device can be prevented by inserting an insulating layer between the semiconducting channel and the substrate. Similarly, source/drain-to-substrate leakage in a FinFET device can be prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. The insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. If an array of semiconducting fins is made up of a multi-layer stack, the bottom material can be removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material can then be filled in with oxide to better support the fins and to isolate the array of fins from the substrate. The resulting FinFET device is fully substrate-isolated in both the gate region and the source/drain regions.

Abstract translation: 可以通过在半导体沟道和衬底之间插入绝缘层来防止FinFET器件中的沟道对衬底的泄漏。 类似地，通过在源极/漏极区域和衬底之间插入绝缘层，可以防止FinFET器件中的源极/漏极到衬底的泄漏。 绝缘层在物理和电气上隔离了衬底的导电路径，从而防止电流泄漏。 如果半导体翅片的阵列由多层堆叠构成，则可以去除底部材料，从而产生悬浮在硅表面上方的翅片阵列。 然后可以用氧化物填充剩下的顶部翅片材料之下的产生的间隙，以更好地支撑翅片并将翅片阵列与基底隔离开。 所得到的FinFET器件在栅极区域和源极/漏极区域中完全衬底隔离。

公开(公告)号：US09437504B2

公开(公告)日：2016-09-06

申请号：US14802407

申请日：2015-07-17

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu ,  Balasubramanian Pranatharthiharan ,  Shom Ponoth

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/6653 ,  H01L29/6656

Abstract: On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.

Abstract translation: 在第一半导体材料基板上沉积由第二半导体材料形成的上覆牺牲层。 在第一区域中，在牺牲层上形成第一半导体材料区域。 在第二区域中，在牺牲层上形成第二半导体材料区域。 图案化第一半导体材料区域以限定第一FinFET鳍片。 图案化第二半导体材料区域以限定第二FinFET鳍片。 翅片各自被盖和侧壁间隔物覆盖。 然后选择性地去除由第二半导体材料形成的牺牲层，以在第一和第二FinFET鳍片下面形成开口（这些鳍片由侧壁间隔件支撑）。 然后每个翅片下面的开口填充有用于将鳍片的半导体材料与衬底隔离的介电材料。