公开(公告)号：US20220115077A1

公开(公告)日：2022-04-14

申请号：US17558123

申请日：2021-12-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Chama Ameziane El Hassani

IPC: G11C16/32 ,  G11C16/10

Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.

公开(公告)号：US11238944B2

公开(公告)日：2022-02-01

申请号：US16824268

申请日：2020-03-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Chama Ameziane El Hassani

IPC: G11C16/32 ,  G11C16/10

Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.

公开(公告)号：US11120878B2

公开(公告)日：2021-09-14

申请号：US16857937

申请日：2020-04-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

Abstract: A method for programming a non-volatile memory (NVM) and an integrated circuit is disclosed. In an embodiment an integrated circuit includes a memory plane organized into rows and columns of memory words, each memory word comprising memory cells and each memory cell including a state transistor having a control gate and a floating gate and write circuitry configured to program a selected memory word during a programming phase by applying a first nonzero positive voltage to control gates of the state transistors of the memory cells that do not belong to the selected memory word.

公开(公告)号：US20210242679A1

公开(公告)日：2021-08-05

申请号：US17165557

申请日：2021-02-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H02H9/04

Abstract: The present disclosure relates to a device including a rectifying bridge including: a branch connected between first and second nodes; another branch including first and second MOS transistors series-connected between the first and second nodes and having their sources coupled together; a resistor connecting the gate of the first transistor to the second node; another resistor connecting the gate of the second transistor and the first node; and for each transistor, a circuit including first and second terminals respectively connected to the drain and to the gate of the transistor, and being configured to electrically couple its first and second terminals when a voltage between the first terminal of the circuit and the first terminal of the other circuit is greater than a threshold of the circuit.

公开(公告)号：US20190341114A1

公开(公告)日：2019-11-07

申请号：US16511703

申请日：2019-07-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/14 ,  G11C16/04 ,  G11C8/14 ,  G11C8/12 ,  G11C16/08 ,  G11C8/08 ,  G11C5/02 ,  G11C8/10

Abstract: A non-volatile memory device includes a substrate, a plurality of memory words, a control block, a first electrically-conducting link, and a plurality of second electrically-conducting links. The substrate includes a substantially planar surface. The memory words include B memory words disposed at the substantially planar surface. The control block includes B control elements disposed at the substantially planar surface. The first electrically-conducting link is disposed in a first plane parallel to the substantially planar surface. The first electrically-conducting link connects one of the B control elements to a memory word of the memory words. The plurality of second electrically-conducting links includes B-1 second electrically-conducting links respectively connecting B-1 remaining control elements to B-1 corresponding memory words of the plurality of memory words. The B-1 second electrically-conducting links are disposed above the first plane and physically extend at least partially over at least two memory words of the memory words.

公开(公告)号：US10304524B2

公开(公告)日：2019-05-28

申请号：US15630614

申请日：2017-06-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: H01L29/788 ,  G11C11/41 ,  G11C11/412 ,  G11C14/00 ,  G11C16/04 ,  H01L27/11 ,  H01L23/522 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51

Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

公开(公告)号：US10186320B2

公开(公告)日：2019-01-22

申请号：US15659891

申请日：2017-07-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista ,  Victorien Brecte

IPC: G11C7/00 ,  G11C16/26 ,  G11C7/06 ,  G11C16/04 ,  G11C16/24

Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

公开(公告)号：US20180300085A1

公开(公告)日：2018-10-18

申请号：US15900481

申请日：2018-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

Abstract: A method of writing in a memory of the EEPROM type includes, in the presence of a string of new bytes to be written in the memory plane in at least one destination memory word already containing old bytes, a verification for each destination memory word whether or not the old bytes of this destination memory word must all be replaced with new bytes. The method also includes a reading of the old bytes of this destination memory word only if the old bytes must not all be replaced with new bytes.

公开(公告)号：US20180268901A1

公开(公告)日：2018-09-20

申请号：US15984779

申请日：2018-05-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/04 ,  H01L27/11521 ,  G11C16/10 ,  G11C16/14 ,  H01L29/788 ,  H01L27/11526

CPC classification number: G11C16/0408 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/7883

Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

公开(公告)号：US10043741B2

公开(公告)日：2018-08-07

申请号：US15380894

申请日：2016-12-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Guilhem Bouton

IPC: G01R31/26 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02 ,  H01L21/66

Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.