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公开(公告)号：US09460761B2
公开(公告)日：2016-10-04
申请号：US14751701
申请日：2015-06-26
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Francesco La Rosa
Abstract: A sense amplifier includes: two detection inputs, a latch circuit including two sections coupled to each other and each supplying a data signal. Each section is respectively powered by a P-channel control transistor, having a gate terminal receiving a control signal linked to a respective detection input of the two detection inputs. The sense amplifier includes a control circuit configured to reduce each of the control signals to a sufficiently low voltage to put the corresponding control transistor to the on state, when the control signal reaches a reference voltage. The latch circuit is activated to supply one of the data signals when a corresponding one of the control transistors is in the on state.
Abstract translation: 读出放大器包括：两个检测输入端，一个锁存电路，包括彼此耦合的两个部分，并且各自提供一个数据信号。 每个部分分别由P沟道控制晶体管供电，其具有接收与两个检测输入的相应检测输入链接的控制信号的栅极端子。 读出放大器包括控制电路，其被配置为当控制信号达到参考电压时，将每个控制信号减小到足够低的电压以将相应的控制晶体管置于导通状态。 当对应的一个控制晶体管处于导通状态时，锁存电路被激活以提供数据信号之一。
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42.发明授权公开(公告)号：US08901634B2
公开(公告)日：2014-12-02
申请号：US13786213
申请日：2013-03-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francesco La Rosa , Yoann Goasduff , Stephan Niel , Arnaud Regnier
IPC: H01L29/788 , G11C16/04 , H01L29/66 , H01L27/115
CPC classification number: H01L29/7889 , G11C16/0425 , G11C16/0483 , G11C16/14 , H01L27/11524 , H01L29/66825
Abstract: The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.
Abstract translation: 本公开涉及一种集成电路，其包括形成在半导体衬底中的至少两个存储单元和与存储单元的选择晶体管共同的掩埋栅极。 掩埋栅极具有在选择晶体管的垂直沟道区域的前面延伸的第一深度的第一部分，以及大于深入埋入源极线的第一深度的至少第二深度的第二部分。 掩埋栅极的下侧由形成选择晶体管的源极区域的掺杂区域界定，并且在埋入栅极的第二部分穿入埋入源极线的水平面到达掩埋源极线，由此源极区域 耦合到埋地源线。
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公开(公告)号：US20130250700A1
公开(公告)日：2013-09-26
申请号：US13786197
申请日：2013-03-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francesco La Rosa
IPC: H01L29/788 , G11C16/04 , H01L29/66
CPC classification number: H01L29/788 , G11C16/0425 , G11C16/0433 , G11C16/10 , G11C16/16 , H01L27/11524 , H01L29/66825
Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.
Abstract translation: 本公开涉及一种在半导体衬底上包括非易失性存储器的集成电路。 集成电路包括注入衬底深度的掺杂隔离层，隔离的导电沟槽到达隔离层并形成存储单元的选择晶体管的栅极，垂直于导电沟槽并到达隔离层的隔离沟槽，并且导线平行 到导电沟槽，在衬底上延伸并形成存储器单元的电荷累积晶体管的控制栅极。 隔离沟槽和隔离的导电沟槽限定了衬底中的多个微型阱，所述微型阱彼此电隔离，每个具有浮置电势并且包括两个存储单元。
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公开(公告)号：US20130229875A1
公开(公告)日：2013-09-05
申请号：US13786202
申请日：2013-03-05
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Francesco La Rosa , Olivier Pizzuto , Stephan Niel , Philippe Boivin , Pascal Fornara , Laurent Lopez , Arnaud Regnier
CPC classification number: G11C16/26 , G11C8/12 , G11C11/5642 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/24 , H01L27/11524 , H01L27/11556 , H01L29/42328 , H01L29/7881
Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.
Abstract translation: 本公开涉及一种读取和写入存储单元的方法，每个存储单元包括与选择晶体管串联的电荷累积晶体管，包括将选择电压施加到存储器单元的选择晶体管的栅极; 将读取电压施加到存储单元的电荷累积晶体管的控制栅极; 将选择电压施加到耦合到相同位线的第二存储器单元的选择晶体管的栅极; 以及向第二存储单元的电荷累积晶体管的控制栅极施加抑制电压，以保持晶体管处于阻塞状态。
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公开(公告)号：US20130057298A1
公开(公告)日：2013-03-07
申请号：US13669732
申请日：2012-11-06
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francesco La Rosa
IPC: G01R27/26
CPC classification number: G01R27/2605 , G06F3/0416 , G06F3/044
Abstract: The disclosure relates to a method for characterizing or measuring a capacitance, comprising: linking the capacitance to a first mid-point of a first capacitive divider bridge, applying to the divider bridge a bias voltage, maintaining the voltage of the first mid-point near a reference voltage, discharging a second mid-point of a second divider bridge in parallel with the first by means of a constant current, and measuring the time for a voltage of the second mid-point to become equal to the voltage of the first mid-point. The disclosure may be applied in particular to the control of a touch screen display.
Abstract translation: 本发明涉及一种用于表征或测量电容的方法，包括：将电容连接到第一电容分压器桥的第一中点，将分压电桥施加偏置电压，将第一中点的电压保持在接近 参考电压，通过恒定电流将与第一分压器并联的第二分压电桥的第二中点放电，并且测量第二中点的电压的时间变得等于第一中间电压的电压 -点。 本公开可以特别地应用于触摸屏显示器的控制。
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Patent Agency Ranking
公开(公告)号：US12198756B2
公开(公告)日：2025-01-14
申请号：US18158232
申请日：2023-01-23
Inventor： Antonino Conte , Francesco La Rosa
Abstract: Unclonable function circuitry includes a plurality of pairs of phase-change memory cells in a virgin state, and sensing circuitry coupled to the plurality of pairs of phase-change memory cells in the virgin state. The sensing circuitry identifies a subset of the plurality of pairs of phase-change memory cells in the virgin state based on a reliability mask. Signs of differences of effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state are sensed by the sensing circuitry. The sensing circuitry generates a string of bits based on the sensed signs of differences in the effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state. Processing circuitry coupled to the unclonable function circuitry, in operation, executes one or more operations using the generated string of bits.
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公开(公告)号：US11615857B2
公开(公告)日：2023-03-28
申请号：US17224024
申请日：2021-04-06
Inventor： Francesco La Rosa , Enrico Castaldo , Francesca Grande , Santi Nunzio Antonino Pagano , Giuseppe Nastasi , Franco Italiano
Abstract: A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.
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公开(公告)号：US20230018738A1
公开(公告)日：2023-01-19
申请号：US17812122
申请日：2022-07-12
Inventor： Francesco La Rosa , Marco Bildgen
IPC: G11C16/04 , H01L27/11524 , G11C16/08 , G11C16/10 , G11C16/26
Abstract: In an embodiment a noon-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processor configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.
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49.发明授权公开(公告)号：US11546177B2
公开(公告)日：2023-01-03
申请号：US16784495
申请日：2020-02-07
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francesco La Rosa
Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of floating gate transistor pairs, floating gate transistors of the set of floating gate transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of floating gate transistors of floating gate transistor pairs of the set of floating gate transistor pairs, and to identify a floating gate transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable floating gate transistor pair; and a write circuit configured to shift the effective threshold voltage of a floating gate transistor of the unreliable floating gate transistor pair to be inside the common random distribution.
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公开(公告)号：US11171644B2
公开(公告)日：2021-11-09
申请号：US17207382
申请日：2021-03-19
Inventor： Antonino Conte , Francesco Tomaiuolo , Francesco La Rosa
Abstract: An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.
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