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公开(公告)号：US09964976B2
公开(公告)日：2018-05-08
申请号：US15596895
申请日：2017-05-16
发明人： Antonino Conte , Carmelo Paolino
摘要： A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.
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42.发明申请公开(公告)号：US20170278552A1
公开(公告)日：2017-09-28
申请号：US15620325
申请日：2017-06-12
CPC分类号： G11C7/062 , G11C7/1051 , G11C7/12 , G11C16/24 , G11C16/28 , G11C2207/002
摘要： A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascade configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.
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43.发明授权公开(公告)号：US09697896B2
公开(公告)日：2017-07-04
申请号：US14623300
申请日：2015-02-16
CPC分类号： G11C13/0069 , G11C8/04 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0061 , G11C13/0097 , G11C2213/79
摘要： A phase change non-volatile memory device has a memory array with a plurality of memory cells arranged in rows and columns, a column decoder and a row decoder designed to select columns, and, respectively, rows of the memory array during operations of programming of corresponding memory cells. A control logic, coupled to the column decoder and the row decoder, is designed to execute a sequential programming command, to control the column decoder and row decoder to select one column of the memory array and execute sequential programming operations on a desired block of memory cells belonging to contiguous selected rows of the selected column.
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公开(公告)号：US09684324B2
公开(公告)日：2017-06-20
申请号：US14969103
申请日：2015-12-15
发明人： Antonino Conte , Carmelo Paolino
摘要： A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.
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公开(公告)号：US08981741B2
公开(公告)日：2015-03-17
申请号：US13770047
申请日：2013-02-19
CPC分类号： G05F1/10 , G06K19/0713 , G06K19/0715 , H02M3/07 , H02M3/1584
摘要： A voltage regulator has an input terminal for receiving a supply voltage and an output terminal for providing a regulated voltage and a regulated current. Furthermore, the voltage regulator includes a regulator for generating the regulated voltage and the regulated current according to a regulation of the supply voltage. The regulator includes a plurality of regulation branches arranged between the input terminal and the output terminal, each one for providing an output voltage used for obtaining the regulated voltage and for providing an output current contributing to define the regulated current. The regulation branches are partitioned into a plurality of subsets each one including components adapted to operate within a corresponding maximum voltage different from the maximum voltage of the other subsets. In addition, the regulator includes a selector for selectively enabling the regulation branches according to an indicator of the supply voltage.
摘要翻译： 电压调节器具有用于接收电源电压的输入端子和用于提供调节电压和调节电流的输出端子。 此外，电压调节器包括用于根据电源电压的调节产生调节电压和调节电流的调节器。 调节器包括布置在输入端子和输出端子之间的多个调节分支，每个调节分支用于提供用于获得调节电压的输出电压并且用于提供有助于限定调节电流的输出电流。 调节分支被划分成多个子集，每个子集包括适于在不同于其他子集的最大电压的对应最大电压内操作的组件。 此外，调节器包括一个选择器，用于根据电源电压的指示器选择性地启用调节分支。
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公开(公告)号：US20240088875A1
公开(公告)日：2024-03-14
申请号：US18451272
申请日：2023-08-17
CPC分类号： H03K3/0315 , H03K3/011
摘要： An electronic system is configured to generate a sequential logic signal. The electronic system includes a first ring oscillator including a first plurality of cascaded inverter stages. A combinational logic circuit is configured to generate the sequential logic signal by combining signals at the output terminals of at least two of the inverter stages of the first ring oscillator. The electronic system further includes a second ring oscillator including a second plurality of cascaded inverter stages. A bias current source is configured to supply the inverter stages of the second ring oscillator with a bias current, and a first voltage is generated at the inverter stages of the second ring oscillator. A voltage follower is configured to supply the inverter stages of the first ring oscillator with a second voltage corresponding to the first voltage generated at the inverter stages of the second ring oscillator.
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公开(公告)号：US20230283271A1
公开(公告)日：2023-09-07
申请号：US18157977
申请日：2023-01-23
发明人： Antonino Conte , Marco Ruta , Michelangelo Pisasale , Agatino Massimo Maccarrone , Francesco Tomaiuolo
CPC分类号： H03K5/24 , H03K3/0315
摘要： A system a ring oscillator configured to produce a set of clock signals having the same clock period and a mutual time delay between respective clock signal edges. Comparator circuits are coupled to first and second input nodes and produce a set of comparison signals according to a respective sequence of comparison phases. A set of synchronization circuits is coupled to the ring oscillator and to the plurality of comparator circuits. The synchronization circuits allot, to each one of the comparator circuits, respective time windows for communication over respective communication lines of the comparison signals. The respective time windows are synchronized based on the clock signals. A multiplexer couples the respective communication lines to an output line to sequentially enable each of the comparator circuits to sequentially output respective comparison signals over the output line for the respective time windows thereby forming a composite comparison signal evolving over time.
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公开(公告)号：US20210349489A1
公开(公告)日：2021-11-11
申请号：US16868799
申请日：2020-05-07
发明人： Antonino Conte
IPC分类号： G05F3/26
摘要： An apparatus includes a current mirror coupled to an output of an amplifier through control switches, a plurality of capacitors, each of which is coupled to a common node of a leg of the current mirror and a corresponding control switch, a first dipole coupled to a first input of an amplifier, a second dipole coupled to a second input of the amplifier, a third dipole coupled to an output of the apparatus configured to generate the bandgap reference voltage, and groups of switches coupled between the current mirror and the dipoles.
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49.发明授权公开(公告)号：US10720210B2
公开(公告)日：2020-07-21
申请号：US16717652
申请日：2019-12-17
发明人： Antonino Conte
摘要： A phase-change memory device includes a memory array including a first memory cell and a second memory cell, each comprising a phase-change element and a selector, connected respectively to a first local bitline and a second local bitline, which are in turn connected, respectively, to a first main bitline and a second main bitline. The parasitic capacitance of the main bitlines is precharged at a supply voltage. When the local bitlines are selected to access a respective logic datum stored in the phase-change element, the parasitic capacitance of the local bitlines is first charged using the charge previously stored in the parasitic capacitance of the main bitlines and then discharged through the respective phase-change elements. Reading of the logic datum is made by comparing the discharge times.
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公开(公告)号：US20200058360A1
公开(公告)日：2020-02-20
申请号：US16104001
申请日：2018-08-16
摘要： A sense structure includes: a sense amplifier core configured to compare a measurement current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor.
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