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1.发明授权公开(公告)号：US09697896B2
公开(公告)日：2017-07-04
申请号：US14623300
申请日：2015-02-16
CPC分类号： G11C13/0069 , G11C8/04 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0061 , G11C13/0097 , G11C2213/79
摘要： A phase change non-volatile memory device has a memory array with a plurality of memory cells arranged in rows and columns, a column decoder and a row decoder designed to select columns, and, respectively, rows of the memory array during operations of programming of corresponding memory cells. A control logic, coupled to the column decoder and the row decoder, is designed to execute a sequential programming command, to control the column decoder and row decoder to select one column of the memory array and execute sequential programming operations on a desired block of memory cells belonging to contiguous selected rows of the selected column.
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2.发明授权Error correction in memory devices by multiple readings with different references 有权通过不同参考的多个读数对存储器件进行错误校正公开(公告)号：US09430328B2
公开(公告)日：2016-08-30
申请号：US14597845
申请日：2015-01-15
发明人： Antonino Conte , Kailash Khairnar
CPC分类号： G06F11/1068 , G06F11/08 , G06F11/1048 , G11C13/0004 , G11C13/004 , G11C29/52 , G11C2013/0054
摘要： A memory device may include memory cells. The method may include receiving a request of reading a selected data word associated with a selected code word stored with an error correction code, and reading a first code word representing a first version of the selected code word by comparing a state of each selected memory cell with a first reference. The method may include verifying the first code word, setting the selected code word according to the first code word in response to a positive verification, reading at least one second code word representing a second version of the selected code word, verifying the second code word, and setting the selected code word according to the second code word in response to a negative verification of the first code word and to a positive verification of the second code word.
摘要翻译： 存储器件可以包括存储器单元。 该方法可以包括：接收读取与通过纠错码存储的所选码字相关联的所选择的数据字的请求，以及通过比较所选择的存储单元的状态来读取表示所选码字的第一版本的第一码字 第一个参考。 该方法可以包括验证第一代码字，响应于正验证，根据第一代码字设置所选择的代码字，读取表示所选代码字的第二版本的至少一个第二代码字，验证第二代码字 并且响应于第一代码字的否定验证和第二代码字的肯定验证，根据第二代码字设置所选择的代码字。
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公开(公告)号：US12107591B2
公开(公告)日：2024-10-01
申请号：US18054333
申请日：2022-11-10
发明人： Agatino Massimo Maccarrone , Antonino Conte , Francesco Tomaiuolo , Michelangelo Pisasale , Marco Ruta
IPC分类号： H03M1/06
CPC分类号： H03M1/0604
摘要： In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.
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公开(公告)号：US11171644B2
公开(公告)日：2021-11-09
申请号：US17207382
申请日：2021-03-19
摘要： An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.
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公开(公告)号：US10818368B2
公开(公告)日：2020-10-27
申请号：US16294386
申请日：2019-03-06
IPC分类号： G11C8/08 , G11C16/34 , G11C5/14 , G11C16/20 , H03K19/00 , H03K19/0175 , G11C8/06 , G11C13/00 , H03K19/0185 , G11C8/10
摘要： A level shifter circuit configured to shift an input signal switching within a first voltage range to generate a first output signal correspondingly switching within a second voltage range higher than the first voltage range. The level shifter circuit including a latching core having latching input and output terminals and a supply line configured to be supplied by a supply voltage, and a reference line configured to be coupled to a reference voltage. Capacitive coupling elements are coupled to the latching input and output terminals of the latching core. A driving stage is configured to bias the capacitive coupling elements with biasing signals generated based on the input signal. A decoupling stage is configured to be driven by the driving stage through the capacitive coupling elements to decouple the supply line from the supply voltage and the reference line from the reference voltage during switching of the input signal.
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公开(公告)号：US20190287633A1
公开(公告)日：2019-09-19
申请号：US16294386
申请日：2019-03-06
摘要： A level shifter circuit configured to shift an input signal switching within a first voltage range to generate a first output signal correspondingly switching within a second voltage range higher than the first voltage range. The level shifter circuit including a latching core having latching input and output terminals and a supply line configured to be supplied by a supply voltage, and a reference line configured to be coupled to a reference voltage. Capacitive coupling elements are coupled to the latching input and output terminals of the latching core. A driving stage is configured to bias the capacitive coupling elements with biasing signals generated based on the input signal. A decoupling stage is configured to be driven by the driving stage through the capacitive coupling elements to decouple the supply line from the supply voltage and the reference line from the reference voltage during switching of the input signal.
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公开(公告)号：US20180003761A1
公开(公告)日：2018-01-04
申请号：US15387370
申请日：2016-12-21
申请人： STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
CPC分类号： G01R31/028 , G01R31/2882 , G04F10/10
摘要： A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.
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公开(公告)号：US09413380B2
公开(公告)日：2016-08-09
申请号：US14638246
申请日：2015-03-04
发明人： Antonino Conte , Maria Giaquinta
CPC分类号： G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
摘要： A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.
摘要翻译： 数模转换器（DAC）可以包括提供第一模拟值的转换块。 DAC还可以包括用于接收第一模拟值并提供由放大因子放大的第二模拟值的放大块。 放大块可以包括用于接收第一模拟值的第一输入端，第二输入端和用于提供第二模拟值的输出端。 放大块还可以包括第一电容元件和第二电容元件。 第一和第二电容元件可以确定放大系数。 放大块还可以包括用于在第二电容元件的第一端子处恢复电荷的控制单元，并且基于该第二模拟值。
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9.发明授权Driving stage for phase change non-volatile memory devices provided with auto-calibration feature 有权具有自动校准功能的相变非易失性存储器件的驱动级公开(公告)号：US08942033B2
公开(公告)日：2015-01-27
申请号：US13774181
申请日：2013-02-22
CPC分类号： G11C13/0004 , G11C5/145 , G11C5/147 , G11C13/0038 , G11C13/0069
摘要： A driving stage for a phase change non-volatile memory device may include an output driving unit, which supplies an output driving current during programming of a memory cell, a driving-control unit, which receives an input current and generates a first control signal for controlling supply of the output driving current in such a way that a value thereof has a desired relation with the input current, and a level-shifter element, which carries out a level shift of a voltage of the first control signal for supplying to the output driving unit a second control signal, having a voltage value that is increased with respect to, and is a function of, the first control signal. A calibration unit may carry out an operation of updating of the value of a shift voltage across the level-shifter element, as the value of the input current varies.
摘要翻译： 用于相变非易失性存储器件的驱动级可以包括输出驱动单元，其在存储单元的编程期间提供输出驱动电流;驱动控制单元，其接收输入电流并产生第一控制信号， 控制输出驱动电流的供给，使得其值与输入电流具有期望的关系;电平移动元件，其执行用于提供给输出的第一控制信号的电压的电平偏移 驱动单元具有第二控制信号，其具有相对于第一控制信号增加并且是第一控制信号的函数的电压值。 校准单元可以执行更新跨越电平移位器元件的移位电压的值的操作，因为输入电流的值变化。
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公开(公告)号：US12057180B2
公开(公告)日：2024-08-06
申请号：US17934102
申请日：2022-09-21
CPC分类号： G11C16/3445 , G11C16/14 , G11C16/26 , G11C16/3459 , G11C16/349 , H10B41/30 , H10B41/40
摘要： In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.
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