公开(公告)号：US11921664B2

公开(公告)日：2024-03-05

申请号：US18077406

申请日：2022-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsung Kim ,  Jangwoo Lee ,  Seonkyoo Lee ,  Chiweon Yoon ,  Jeongdon Ihm

IPC: G06F3/06 ,  G06F13/40 ,  G06F18/214

CPC classification number: G06F13/4072 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0679 ,  G06F18/214

Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.

公开(公告)号：US20230223941A1

公开(公告)日：2023-07-13

申请号：US17932023

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo Lee ,  Yoo-Chang Sung ,  Jeongdon Ihm ,  Hojun Chang ,  Jinseok Heo

IPC: H03K21/02 ,  G11C11/4076 ,  G11C11/4093 ,  H03K23/40

CPC classification number: H03K21/026 ,  G11C11/4076 ,  G11C11/4093 ,  H03K23/40

Abstract: Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.

公开(公告)号：US11475955B2

公开(公告)日：2022-10-18

申请号：US17393784

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junha Lee ,  Seonkyoo Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: G11C16/06 ,  H01L23/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

公开(公告)号：US11217283B2

公开(公告)日：2022-01-04

申请号：US17012845

申请日：2020-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junha Lee ,  Seonkyoo Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: G11C7/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

公开(公告)号：US20200167298A1

公开(公告)日：2020-05-28

申请号：US16425105

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manjae Yang ,  Jangwoo Lee ,  Hwasuk Cho ,  Jeongdon Ihm

IPC: G06F13/16 ,  G06F3/06 ,  G11C7/10

Abstract: An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an external chip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal.

公开(公告)号：US09886379B2

公开(公告)日：2018-02-06

申请号：US14668015

申请日：2015-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunjin Kim ,  Kitae Park ,  Seonkyoo Lee ,  Jeongdon Ihm ,  Youngjin Jeon

IPC: G06F12/02 ,  G11C16/10 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F12/0246 ,  G06F13/1673 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/1072 ,  G11C16/102

Abstract: A solid state drive includes a nonvolatile memory, a random access memory, and a memory controller. The nonvolatile memory contains a plurality of nonvolatile memories chips and a buffer chip. The memory controller is formed of an internal bus, a host interface, a memory interface, a buffer control circuit, and a processor.

公开(公告)号：US09633743B2

公开(公告)日：2017-04-25

申请号：US14600353

申请日：2015-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jangwoo Lee ,  Kyoungtae Kang ,  Taesung Lee ,  Jeongdon Ihm

IPC: G11C16/04 ,  G11C16/32 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.

公开(公告)号：US09147489B2

公开(公告)日：2015-09-29

申请号：US14077769

申请日：2013-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyun Kim ,  Youngsun Min ,  Bilal Ahmad Janjua ,  Jeongdon Ihm

IPC: G11C16/06 ,  G11C16/30 ,  G11C16/04 ,  G11C16/12

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/12

Abstract: A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a PMOS transistor configured to transfer the second driving voltage provided to a first terminal of the PMOS transistor from the depletion type NMOS transistor to a second terminal of the PMOS transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the PMOS transistor.

Abstract translation: 非易失性存储器件的高电压开关包括耗尽型NMOS晶体管，其配置为响应于高电压开关的输出信号而切换第二驱动电压; 至少一个反相器，被配置为将高压开关的输入信号的电压转换为第一驱动电压或接地电压，其中从外部装置接收第一和第二驱动电压; 以及PMOS晶体管，被配置为响应于所述至少一个反相器的输出，将提供给所述PMOS晶体管的第一端子的所述第二驱动电压从所述耗尽型NMOS晶体管传送到所述PMOS晶体管的第二端子作为所述输出信号， 其中所述至少一个反相器的输出被传送到所述PMOS晶体管的栅极端子。