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    WASHING MACHINE AND CONTROLLING METHOD OF WASHING MACHINE
    42.
    发明公开
    WASHING MACHINE AND CONTROLLING METHOD OF WASHING MACHINE 审中-公开

    公开(公告)号：US20230416964A1

    公开(公告)日：2023-12-28

    申请号：US18207927

    申请日：2023-06-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngjin CHO ,  Kanghyun LEE ,  Dongpil SEO ,  Jaeryong PARK

    IPC: D06F33/42 ,  D06F33/47

    CPC classification number: D06F33/42 ,  D06F33/47 ,  D06F2103/42

    Abstract: A washing machine includes: a housing; a tub inside the housing; a case connected with the tub; a filter attachable to or detachable from the case; a filtering flow path formed to pass through a portion of the filter; a bypass flow path formed to bypass the portion of the filter; and at least one sensor configured to obtain information about a state of the filter. The washing machine includes; a flow path switching device configured to guide water entered into the case to the filtering flow path or the bypass flow path; and a controller configured to control the flow path switching device to guide the water based on the obtained information about the state of the filter.

    VARIABLE RESISTANCE MEMORY DEVICE
    43.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE 有权

    公开(公告)号：US20230078373A1

    公开(公告)日：2023-03-16

    申请号：US17989085

    申请日：2022-11-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Jungho YOON ,  Youngjin CHO

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer and a second layer. The first layer is formed of a first material. The second layer is on the first layer and formed of a second material having a density different from a density of the first material. The first conductive element and a second conductive element are located on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer. The current path is in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

    WASHING MACHINE DRUM ASSEMBLY, WASHING MACHINE INCLUDING THE SAME, AND METHOD OF PRODUCING THE SAME
    44.
    发明申请
    WASHING MACHINE DRUM ASSEMBLY, WASHING MACHINE INCLUDING THE SAME, AND METHOD OF PRODUCING THE SAME 有权

    公开(公告)号：US20210062387A1

    公开(公告)日：2021-03-04

    申请号：US16734736

    申请日：2020-01-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngjin CHO ,  Kanghyun LEE ,  Jeoungkyo JEOUNG

    IPC: D06F37/22 ,  D06F37/04 ,  D06F21/04 ,  B21D51/18

    Abstract: A washing machine drum assembly includes: a drum having a hollow cylindrical shape, including a front end flange formed at a front end of the drum and a rear end flange formed at a rear end of the drum, and including a plurality of coupling holes formed adjacent to the rear end flange; a front surface plate mounted on the front end of the drum; and a rear surface plate mounted on the rear end of the drum and including a plurality of rear surface holes corresponding to the plurality of coupling holes of the drum, wherein a rear end positioning mechanism configured to position the rear surface plate with respect to the drum is formed in the rear end flange of the drum and the rear surface plate.

    MEMORY CONTROLLER WITH HIGH DATA RELIABILITY, A MEMORY SYSTEM HAVING THE SAME, AND AN OPERATION METHOD OF THE MEMORY CONTROLLER
    45.
    发明申请
    MEMORY CONTROLLER WITH HIGH DATA RELIABILITY, A MEMORY SYSTEM HAVING THE SAME, AND AN OPERATION METHOD OF THE MEMORY CONTROLLER 有权

    公开(公告)号：US20210055985A1

    公开(公告)日：2021-02-25

    申请号：US16882601

    申请日：2020-05-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jeongho LEE ,  Youngjin CHO ,  Seungwon LEE

    IPC: G06F11/10 ,  H03M13/09 ,  H03M13/25

    Abstract: A memory controller including: a fault determination circuit to receive first parity, second parity, and data read out from a first row of a memory device, and determine, based on a result of a first error detection operation using the first parity and a result of a second error detection operation using the second parity, whether the first row is faulty; a parity storage circuit to store a repair parity for repairing a fault of a row of a plurality of rows of the memory device, wherein the plurality of rows constitutes a repair unit, and wherein the repair unit includes the first row and one or more second rows; and a recovery circuit to repair a fault of the first row by using data of at least one of the second rows and the repair parity, when the first row is determined to be a faulty row.

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