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253 条记录 (耗时 0.034 秒)

    Carbon implant for workfunction adjustment in replacement gate transistor
    42.
    发明授权
    Carbon implant for workfunction adjustment in replacement gate transistor 有权
    用于替换栅极晶体管功能调整的碳植入物

    公开(公告)号：US08513081B2

    公开(公告)日：2013-08-20

    申请号：US13272349

    申请日：2011-10-13

    申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

    发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

    IPC分类号： H01L21/336

    CPC分类号： H01L21/2822 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

    摘要： A method includes providing a wafer that has a semiconductor layer having an insulator layer disposed on the semiconductor layer. The insulator layer has openings made therein to expose a surface of the semiconductor layer, where each opening corresponds to a location of what will become a transistor channel in the semiconductor layer disposed beneath a gate stack. The method further includes depositing a high dielectric constant gate insulator layer so as to cover the exposed surface of the semiconductor layer and sidewalls of the insulator layer; depositing a gate metal layer that overlies the high dielectric constant gate insulator layer; and implanting Carbon through the gate metal layer and the underlying high dielectric constant gate insulator layer so as to form in an upper portion of the semiconductor layer a Carbon-implanted region having a concentration of Carbon selected to establish a voltage threshold of the transistor.

    摘要翻译： 一种方法包括提供具有设置在半导体层上的绝缘体层的半导体层的晶片。 绝缘体层具有在其中形成的开口以暴露半导体层的表面，其中每个开口对应于在栅叠层下方的半导体层中将成为晶体管沟道的位置。 该方法还包括沉积高介电常数栅极绝缘体层以覆盖半导体层的暴露表面和绝缘体层的侧壁; 沉积覆盖在高介电常数栅极绝缘体层上的栅极金属层; 以及通过栅极金属层和下面的高介电常数栅极绝缘体层注入碳以便在半导体层的上部形成具有选定的碳浓度的碳注入区域，以建立晶体管的电压阈值。

    Self-aligned carbon electronics with embedded gate electrode
    43.
    发明授权
    Self-aligned carbon electronics with embedded gate electrode 有权
    具有嵌入式栅电极的自对准碳电子器件

    公开(公告)号：US08455365B2

    公开(公告)日：2013-06-04

    申请号：US13111615

    申请日：2011-05-19

    申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

    发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L29/66515 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/0545

    摘要： A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.

    摘要翻译： 一种用于器件制造的器件和方法包括在电介质衬底中形成掩埋栅电极，并且在掩埋栅电极之上构图包括高介电常数层，碳基半导电层和保护层的堆叠。 在叠层上形成的绝缘介电层被打开以在与堆叠相邻的区域中限定凹陷。 蚀刻凹槽以形成空腔并去除高介电常数层的一部分以暴露在掩埋栅电极的相对侧上的碳基半导体层。 导电材料沉积在空腔中以形成自对准的源区和漏区。

    TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES
    44.
    发明申请
    TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES 有权
    采用垂直堆叠自对准碳纳米管的晶体管

    公开(公告)号：US20130130446A1

    公开(公告)日：2013-05-23

    申请号：US13605238

    申请日：2012-09-06

    申请人： Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

    发明人： Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/336 ,  B82Y40/00

    CPC分类号： H01L51/057 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/0045 ,  H01L51/0048 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

    摘要： A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.

    摘要翻译： 形成包括具有第一等电点的第一等电点材料层和具有小于第一等电点的第二等电点的第二等电子材料层的垂直交替堆叠的鳍结构。 第一和第二等电点材料层在具有第一和第二等电点之间的pH的溶液中相反地充电。 通过阴离子表面活性剂将负电荷赋予碳纳米管。 静电引力使得碳纳米管选择性地附着在第一等电点材料层的表面上。 碳纳米管沿翅片结构的水平长度方向自对准地附接到第一等电点材料层。 可以形成晶体管，其采用多个垂直排列的水平碳纳米管作为沟道。

    VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE
    45.
    发明申请
    VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE 有权
    具有不对称门的垂直晶体管

    公开(公告)号：US20130093000A1

    公开(公告)日：2013-04-18

    申请号：US13271812

    申请日：2011-10-12

    申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

    发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

    摘要： A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.

    摘要翻译： 晶体管结构被形成为包括衬底和覆盖衬底的源极; 排水 以及垂直设置在源极和漏极之间的通道。 通道耦合到栅极导体，该栅极导体通过围绕该沟道的栅极电介质材料层围绕该沟道。 栅极导体由具有围绕通道长度的第一部分的第一功函数的第一导电材料和具有围绕通道长度的第二部分的第二功函数的第二导电材料组成。 还公开了制造晶体管结构的方法。 晶体管结构可以表征为具有非对称栅极的垂直场效应晶体管。

    Multiple threshold voltages in field effect transistor devices
    49.
    发明授权
    Multiple threshold voltages in field effect transistor devices 失效
    场效应晶体管器件中的多个阈值电压

    公开(公告)号：US08686514B2

    公开(公告)日：2014-04-01

    申请号：US13560240

    申请日：2012-07-27

    申请人： Dechao Guo ,  Keith Kwong Hon Wong

    发明人： Dechao Guo ,  Keith Kwong Hon Wong

    IPC分类号： H01L27/088

    CPC分类号： H01L29/78696 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795

    摘要： A field effect transistor device includes a first conductive channel disposed on a substrate, a second conductive channel disposed on the substrate, a first gate stack formed on the first conductive channel, the first gate stack including a metallic layer having a first oxygen content, a second gate stack a formed on the second conductive channel, the second gate stack including a metallic layer having a second oxygen, an ion doped source region connected to the first conductive channel and the second conductive channel, and an ion doped drain region connected to the first conductive channel and the second conductive channel.

    摘要翻译： 场效应晶体管器件包括设置在衬底上的第一导电沟道，设置在衬底上的第二导电沟道，形成在第一导电沟道上的第一栅极叠层，第一栅叠层包括具有第一氧含量的金属层， 形成在第二导电沟道上的第二栅极堆叠a，第二栅极堆叠包括具有第二氧的金属层，连接到第一导电沟道和第二导电沟道的离子掺杂源区，以及连接到第二导电沟的离子掺杂漏极区 第一导电沟道和第二导电沟道。