公开(公告)号：US08441045B2

公开(公告)日：2013-05-14

申请号：US13378206

申请日：2011-02-27

申请人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L27/085 ,  H01L29/84 ,  H01L29/80 ,  H01L31/112 ,  H01L29/04

CPC分类号： H01L29/165 ,  H01L21/30608 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7834 ,  H01L29/7849

摘要： The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than 180°, and the first sidewall and the second side wall being roughly symmetrical with respect to a plane parallel to the semiconductor substrate. Embodiments of the present invention are applicable to the stress engineering technology in the semiconductor device manufacturing.

摘要翻译： 本申请公开了一种半导体器件及其制造方法。 其中，所述半导体器件包括：半导体衬底; 嵌入在半导体衬底中的应力器; 设置在所述应力器上的通道区域; 设置在通道区域上的栅极堆叠; 源极/漏极区域，设置在沟道区域的两侧并且嵌入在半导体衬底中; 其中，所述应力器的表面包括顶壁，底壁和侧壁，所述侧壁包括第一侧壁和第二侧壁，所述第一侧壁连接所述顶壁和所述第二侧壁，所述第二侧 连接第一侧壁和底壁的壁，第一侧壁和第二侧壁之间的角度小于180°，第一侧壁和第二侧壁相对于平行于半导体的平面大致对称 基质。 本发明的实施例可应用于半导体器件制造中的应力工程技术。

公开(公告)号：US08426920B2

公开(公告)日：2013-04-23

申请号：US13379111

申请日：2011-08-01

申请人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L27/12

CPC分类号： H01L29/78648

摘要： The present application provides a MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first buried insulating layer on the semiconductor substrate; a back gate formed in a first semiconductor layer which is on the first buried insulating layer; a second buried insulating layer on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is on the second buried insulating layer; a gate on the second semiconductor layer; and electrical contacts on the source/drain regions, the gate and the back gate, wherein the back gate is only under a channel region and one of the source/drain regions and not under the other of the source/drain regions, and a common electrical contact is formed between the back gate and the one of the source/drain regions. The MOSFET improves an effect of suppressing short channel effects by an asymmetric back gate, and reduces a footprint on a wafer by using the common conductive via.

摘要翻译： 本申请提供了一种MOSFET及其制造方法。 MOSFET包括：半导体衬底; 半导体衬底上的第一掩埋绝缘层; 形成在第一掩埋绝缘层上的第一半导体层中的背栅; 在所述第一半导体层上的第二掩埋绝缘层; 源极/漏极区，形成在第二绝缘层上的第二半导体层中; 第二半导体层上的栅极; 以及源极/漏极区域，栅极和背栅极之间的电接触，其中后栅极仅在沟道区域和源极/漏极区域中的一个并且不在源极/漏极区域的另一个之下，并且具有公共 在后栅极和源极/漏极区域之间形成电接触。 MOSFET改善了通过不对称背栅抑制短沟道效应的效果，并且通过使用公共导电通孔来减小晶片上的占位面积。

公开(公告)号：US20130093020A1

公开(公告)日：2013-04-18

申请号：US13580053

申请日：2011-11-18

申请人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/78648

摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.

摘要翻译： 本申请公开了一种MOSFET及其制造方法。 MOSFET形成在SOI晶片上，包括：用于限定半导体层中的有源区的浅沟槽隔离; 半导体层上的栅叠层; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 半导体层中的沟道区，被源极区和漏极区夹持; 半导体衬底中的背栅; 与半导体层和浅沟槽隔离之间的边界重叠的第一虚拟栅极堆叠; 以及在浅沟槽隔离上的第二虚拟栅极堆叠，其中所述MOSFET还包括多个导电通孔，所述多个导电通孔设置在所述栅极堆叠和所述第一虚拟栅极堆叠之间，并分别电连接到所述源极区域和所述漏极区域之间，以及 第一虚拟栅极堆叠和第二虚拟栅极堆叠并且电连接到背栅极。 MOSFET通过虚拟栅极堆叠避免了背栅极和源极/漏极区域之间的短路。

公开(公告)号：US20130093002A1

公开(公告)日：2013-04-18

申请号：US13510407

申请日：2011-11-18

申请人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/78648 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/74 ,  H01L29/66545 ,  H01L29/66772

摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.

摘要翻译： 本公开公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体衬底，所述半导体衬底上的埋入绝缘层以及所述埋入绝缘层上的半导体层; 半导体层上的栅叠层; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 以及位于所述源极区域和所述漏极区域之间的所述半导体层中的沟道区域，其中，所述MOSFET还包括位于所述半导体衬底中并具有作为所述后栅极的下部的第一掺杂区域的背栅极和 第二掺杂区域作为背栅极的上部，并且后栅极的第二掺杂区域与栅极堆叠自对准。 MOSFET可以通过改变背栅的掺杂类型和掺杂浓度来调节阈值电压。

公开(公告)号：US08420489B2

公开(公告)日：2013-04-16

申请号：US12996809

申请日：2010-06-25

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L21/336

CPC分类号： H01L29/4966 ,  H01L21/26586 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/78

摘要： A method of manufacturing a semiconductor device, wherein thermal annealing of the source/drain regions is performed before reverse Halo implantation to form a reverse Halo implantation region. The method comprises: removing the dummy gate to expose the gate dielectric layer, so as to form an opening; performing reverse Halo implantation on the substrate via the opening, so as to form a reverse Halo implantation region in the channel of the device; activating the dopants in the reverse Halo implantation region by annealing; and performing subsequent device processing. Deterioration of the gate stack due to the reverse Halo ions implantation may be avoided by the present invention, such that the reverse Halo ions implantation may be applied to the device with a metal gate stack, and the short channel effects may be alleviated and controlled, thereby the performance of the device is enhanced.

摘要翻译： 一种制造半导体器件的方法，其中在反向光晕注入之前进行源极/漏极区域的热退火以形成反向光晕注入区域。 该方法包括：去除虚拟栅极以露出栅极电介质层，以形成开口; 经由开口在衬底上进行反向光晕注入，以在器件的沟道中形成反向光晕注入区域; 通过退火激活反向卤素注入区域中的掺杂剂; 并执行后续的设备处理。 通过本发明可以避免由于反向卤素离子注入引起的栅极堆叠的劣化，使得可以用金属栅极叠层将相反的Halo离子注入施加到器件，并且可以减轻和控制短沟道效应， 从而增强了设备的性能。

公开(公告)号：US20130082354A1

公开(公告)日：2013-04-04

申请号：US13580966

申请日：2012-05-14

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/36 ,  H01L21/20

CPC分类号： H01L29/785 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66795

摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming a dielectric film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin; and forming a retrograde doped well structure on the inner walls of the first semiconductor fin and the second semiconductor fin, wherein the inner walls thereof are opposite to each other. Correspondingly, the present invention further provides a semiconductor structure. In the present invention, a retrograde doped well structure is formed on the sidewalls of the two semiconductor fins that are opposite to each other, so that the width of the source/drain depletion layer may be effectively reduced, and thereby the short channel effect is reduced.

摘要翻译： 本发明提供一种制造半导体结构的方法，包括以下步骤：提供半导体衬底，在半导体衬底上形成绝缘层，并在绝缘层上形成半导体基底层; 在所述半导体基底层上形成包围所述牺牲层的牺牲层和间隔物，并且通过以所述间隔物作为掩模来蚀刻所述半导体基底层以形成半导体本体; 在所述半导体主体的侧壁上形成电介质膜; 去除位于牺牲层下面的牺牲层和半导体本体以形成第一半导体鳍片和第二半导体鳍片; 以及在所述第一半导体翅片和所述第二半导体翅片的内壁上形成逆向掺杂的阱结构，其中所述内壁彼此相对。 相应地，本发明还提供一种半导体结构。 在本发明中，在两个相互相对的两个半导体鳍片的侧壁上形成逆向掺杂阱结构，从而可以有效地减小源/漏耗尽层的宽度，从而短沟道效应为 减少

公开(公告)号：US20130069041A1

公开(公告)日：2013-03-21

申请号：US13510390

申请日：2011-11-18

申请人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L29/775 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L21/0242 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02507 ,  H01L21/02527 ,  H01L21/02639 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

摘要： A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.

摘要翻译： 提供了具有石墨烯纳米带的MOSFET及其制造方法。 MOSFET包括绝缘基板; 和绝缘基板上的氧化物保护层。 至少一个石墨烯纳米带被嵌入在氧化物保护层中并且具有暴露在氧化物保护层的侧表面的表面。 在所述至少一个石墨烯纳米带的每个中设置有沟道区。 在所述至少一个石墨烯纳米带的每一个中设置源极区和漏极区。 沟道区位于源区和漏区之间。 栅电介质位于至少一个石墨烯纳米带上。 栅极电介质上的栅极导体。 源极和漏极触点分别在氧化物保护层的侧表面上接触源极区域和漏极区域。

公开(公告)号：US20130049138A1

公开(公告)日：2013-02-28

申请号：US13634266

申请日：2011-11-18

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L21/823431

摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a first fin being formed by patterning the semiconductor layer; and a second fin being formed by patterning the semiconductor layer, wherein: top sides of the first and second fins have the same height; bottom sides of the first and second fins adjoin the semiconductor layer; and the second fin is higher than the first fin. According to the present disclosure, a plurality of semiconductor devices with different dimensions can be integrated on the same wafer. As a result, manufacturing process can be shortened and manufacturing cost can be reduced. Furthermore, devices with different driving capabilities can be provided.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 半导体器件包括：半导体层; 通过图案化半导体层形成第一鳍片; 并且通过图案化半导体层形成第二鳍片，其中：第一鳍片和第二鳍片的顶侧具有相同的高度; 第一和第二散热片的底面邻接半导体层; 第二鳍高于第一鳍。 根据本公开，可以将多个具有不同尺寸的半导体器件集成在同一晶片上。 结果，可以缩短制造工序，降低制造成本。 此外，可以提供具有不同驱动能力的装置。

公开(公告)号：US20130032777A1

公开(公告)日：2013-02-07

申请号：US13376237

申请日：2011-08-05

申请人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

发明人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L29/06 ,  H01L21/20 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L29/45 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/7781 ,  H01L29/78618 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0562

摘要： The present invention discloses a semiconductor device and a manufacturing method thereof. The method comprises the steps of providing a substrate on which a graphene layer or carbon nanotube layer is formed; exposing part of the graphene layer or carbon nanotube layer after forming a gate structure on the graphene layer or carbon nanotube layer, wherein the gate structure comprises a gate stack, a spacer and a cap layer, the cap layer is located on the gate stack, and the spacer surrounds the gate stack and the cap layer; epitaxially growing a semiconductor layer on the exposed graphene layer or carbon nanotube layer; and forming a metal contact layer on the semiconductor layer. In the present invention, the semiconductor layer is formed on the graphene layer or carbon nanotube layer, and then the metal contact layer is formed on the semiconductor layer, instead of forming the metal contact layer directly from the graphene layer or carbon nanotube layer. This facilitates to form the self-aligned source and drain contact plugs.

摘要翻译： 本发明公开了一种半导体器件及其制造方法。 该方法包括提供其上形成有石墨烯层或碳纳米管层的基板的步骤; 在石墨烯层或碳纳米管层上形成栅极结构之后暴露部分石墨烯层或碳纳米管层，其中栅极结构包括栅极堆叠，间隔物和覆盖层，盖层位于栅极叠层上， 并且所述间隔件围绕所述栅极堆叠和所述盖层; 在暴露的石墨烯层或碳纳米管层上外延生长半导体层; 以及在所述半导体层上形成金属接触层。 在本发明中，在石墨烯层或碳纳米管层上形成半导体层，然后在半导体层上形成金属接触层，而不是直接从石墨烯层或碳纳米管层形成金属接触层。 这有助于形成自对准的源极和漏极接触插头。

公开(公告)号：US20130015497A1

公开(公告)日：2013-01-17

申请号：US13119074

申请日：2011-02-18

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L29/0847 ,  H01L21/76805 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/78

摘要： An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first region and made of a material different from that of the first region. A method for forming an S/D region is further provided, and the method includes: forming trenches at both sides of a gate stack structure in a substrate; forming a first semiconductor layer, wherein at least a part of the first semiconductor layer is filled into the trenches; and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is made of a material different from that of the first semiconductor layer. A contact hole and a forming method thereof are also provided which may increase the contact area between a contact hole and a contact region, and reduce the contact resistance.

摘要翻译： 提供包括第一区域和第二区域的S / D区域。 第一区域在衬底中具有至少部分厚度。 第二区域形成在第一区域上并且由与第一区域不同的材料制成。 还提供了形成S / D区域的方法，该方法包括：在基板中的栅叠层结构的两侧形成沟槽; 形成第一半导体层，其中所述第一半导体层的至少一部分被填充到所述沟槽中; 以及在所述第一半导体层上形成第二半导体层，其中所述第二半导体层由与所述第一半导体层不同的材料制成。 还提供接触孔及其形成方法，其可以增加接触孔和接触区域之间的接触面积，并降低接触电阻。