公开(公告)号：US20210367078A1

公开(公告)日：2021-11-25

申请号：US16975309

申请日：2019-02-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Hitoshi KUNITAKE ,  Yoko TSUKAMOTO

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66

Abstract: A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, abnormality in shape, or dielectric breakdown is inhibited is provided.
The semiconductor device includes a first region and a second region over the same plane. The first region includes a transistor. The second region includes a dummy transistor. The transistor includes a first wiring layer, a semiconductor layer including an oxide and provided above the first wiring layer, a second wiring layer provided above the semiconductor layer, and a third wiring layer provided above the second wiring layer. The dummy transistor has the same area as one or more selected from the first wiring layer, the second wiring layer, the semiconductor layer, and the third wiring layer.

公开(公告)号：US20210327915A1

公开(公告)日：2021-10-21

申请号：US17365149

申请日：2021-07-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi KATO ,  Masayukl SAKAKURA

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/108

Abstract: A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

公开(公告)号：US20210174857A1

公开(公告)日：2021-06-10

申请号：US17048330

申请日：2019-04-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Hajime KIMURA ,  Atsushi MIYAGUCHI ,  Tatsunori INOUE

IPC: G11C11/405 ,  G06F12/0893 ,  H01L27/108 ,  H01L27/12

Abstract: A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed.

公开(公告)号：US20200336066A1

公开(公告)日：2020-10-22

申请号：US16849339

申请日：2020-04-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuji NISHIJIMA ,  Hidetomo KOBAYASHI ,  Tomoaki ATSUMI ,  Kiyoshi KATO

IPC: H02M3/156 ,  G05B19/048 ,  G06F1/32 ,  G01R19/00 ,  G08B26/00 ,  G08B29/18 ,  H04L12/28 ,  H02M3/158 ,  G01D4/00 ,  H04B1/16 ,  G05B15/02

Abstract: Provided is a structure which is capable of central control of an electric device and a sensor device and a structure which can reduce power consumption of an electric device and a sensor device. A central control system includes at least a central control device, an output unit, and an electric device or a sensor device. The central control device performs arithmetic processing on information transmitted from the electric device or the sensor device and makes the output unit output information obtained by the arithmetic processing. It is possible to know the state of the electric device or the sensor device even apart from the electric device or the sensor device. The electric device or the sensor device includes a transistor which includes an activation layer using a semiconductor with the band gap wider than that of single crystal silicon.

公开(公告)号：US20190287974A1

公开(公告)日：2019-09-19

申请号：US16431778

申请日：2019-06-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO

IPC: H01L27/105 ,  H01L27/108 ,  H01L27/12 ,  H01L27/1156 ,  H01L27/11551 ,  H01L27/11521 ,  H01L27/06

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

公开(公告)号：US20190067336A1

公开(公告)日：2019-02-28

申请号：US16107536

申请日：2018-08-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Masahiko HAYAKAWA ,  Kiyoshi KATO ,  Mitsuaki OSAME

IPC: H01L27/12 ,  H01L33/52 ,  H01L27/32 ,  G02F1/1362 ,  H01L51/52 ,  H01L27/13

Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is fanned so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.

公开(公告)号：US20170309325A1

公开(公告)日：2017-10-26

申请号：US15644905

申请日：2017-07-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Wataru UESUGI ,  Takahiko ISHIZU

IPC: G11C11/4091 ,  G11C7/02 ,  G11C11/4094 ,  H01L27/108 ,  G11C11/4097 ,  G11C5/02

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2213/71 ,  H01L27/10808 ,  H01L27/1225

Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

公开(公告)号：US20170272079A1

公开(公告)日：2017-09-21

申请号：US15610705

申请日：2017-06-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi FUJITA ,  Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Hidetomo KOBAYASHI

IPC: H03K19/177 ,  H03K19/173

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

公开(公告)号：US20170186473A1

公开(公告)日：2017-06-29

申请号：US15390920

申请日：2016-12-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Tomoaki ATSUMI

IPC: G11C11/4074 ,  H01L27/108 ,  H01L29/786 ,  H01L27/115 ,  G11C11/4096 ,  G11C11/4094

CPC classification number: G11C11/4074 ,  G11C5/146 ,  G11C5/147 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4096 ,  H01L27/10805 ,  H01L27/115 ,  H01L28/00 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

公开(公告)号：US20170062482A1

公开(公告)日：2017-03-02

申请号：US15245310

申请日：2016-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Shuhei NAGATSUKA

IPC: H01L27/12 ,  H01L23/544 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L23/544 ,  H01L27/1207 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2223/54453

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

Abstract translation: 提供在其制造过程中不容易被ESD损坏的半导体器件。 带隙大于或等于2.5eV且小于或等于4.2eV，优选大于或等于2.7eV且小于或等于3.5eV的层被提供以与切割线重叠。 在诸如晶体管的半导体器件周围设置一个其带隙大于或等于2.5eV且小于或等于4.2eV，优选大于或等于2.7eV且小于或等于3.5eV的层。 该层可以处于浮置状态或者可以被提供特定的电位。