公开(公告)号：US07071095B2

公开(公告)日：2006-07-04

申请号：US10850763

申请日：2004-05-20

申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC分类号： H01L21/4763

CPC分类号： H01L21/76865 ,  H01L21/02046 ,  H01L21/2855 ,  H01L21/32131 ,  H01L21/76843 ,  H01L21/76862

摘要： A novel process for re-distributing a barrier layer deposited on a single damascene, dual damascene or other contact opening structure. The process includes providing a substrate having a contact opening structure and a metal barrier layer deposited in the contact opening structure, re-sputtering the barrier layer by bombarding the barrier layer with argon ions and metal ions, and re-sputtering the barrier layer by bombarding the barrier layer with argon ions.

摘要翻译： 一种用于重新分布沉积在单个镶嵌，双镶嵌或其他接触开口结构上的阻挡层的新方法。 该方法包括提供具有接触开口结构的衬底和沉积在接触开口结构中的金属阻挡层，通过用氩离子和金属离子轰击阻挡层来重新溅射阻挡层，并通过轰击来重新溅射阻挡层 阻挡层具有氩离子。

公开(公告)号：US20060118962A1

公开(公告)日：2006-06-08

申请号：US11004767

申请日：2004-12-03

申请人： Jui Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

发明人： Jui Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76838 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

摘要翻译： 提出了一种形成集成电路互连结构的方法。 在半导体衬底上形成第一导电线。 导电盖层形成在第一导电线上以提高器件的可靠性。 在导电盖层上形成蚀刻停止层（ESL）。 在ESL上形成层间电介质（IMD）。 通孔和沟槽形成在ESL，IMD和导电盖层中。 在第一导线中形成凹部。 当蚀刻第一电介质时，或者通过诸如氩气溅射的分离工艺，可以通过过蚀刻形成凹部。 形成第二导电线，填充沟槽，开口和凹陷。

公开(公告)号：US20060099802A1

公开(公告)日：2006-05-11

申请号：US10985149

申请日：2004-11-10

申请人： Jing-Cheng Lin ,  Shau-Lin Shue

发明人： Jing-Cheng Lin ,  Shau-Lin Shue

IPC分类号： H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： A semiconductor structure having a via formed in a dielectric layer is provided. The exposed pores of the dielectric material along the sidewalls of the via are partially or completely sealed. Thereafter, one or more barrier layers may be formed and the via may be filled with a conductive material. The barrier layers formed over the sealing layer exhibits a more continuous barrier layer. The pores may be partially or completely sealed by performing, for example, a plasma process in an argon environment.

摘要翻译： 提供了具有形成在电介质层中的通孔的半导体结构。 沿着通孔的侧壁的电介质材料的暴露的孔部分或完全密封。 此后，可以形成一个或多个阻挡层，并且可以用导电材料填充通孔。 形成在密封层之上的阻挡层表现出更连续的阻挡层。 通过在氩气环境中进行例如等离子体处理，可以将孔部分或完全密封。

公开(公告)号：US20050277298A1

公开(公告)日：2005-12-15

申请号：US11201845

申请日：2005-08-11

申请人： Jing Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

发明人： Jing Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L33/00

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

摘要翻译： 提供了一种新的方法和结构，用于创建铜双镶嵌互连。 在电介质层中产生双镶嵌结构，任选地，金属阻挡层沉积在双镶嵌结构的暴露表面上。 沉积铜籽晶层，双镶嵌结构填充铜。 对所制造的铜互连进行退火，之后从电介质去除多余的铜。 对本发明至关重要的是，然后在铜双镶嵌互连件上沉积薄层的氧化物作为覆盖层，然后将蚀刻停止层沉积在氧化物薄层上用于持续的上层金属化。

公开(公告)号：US20050266679A1

公开(公告)日：2005-12-01

申请号：US10995752

申请日：2004-11-23

申请人： Jing-Cheng Lin ,  Shau-Lin Shue

发明人： Jing-Cheng Lin ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76865

摘要： A via having a unique barrier layer structure is provided. In an embodiment, a via is formed by forming a barrier layer in a via. The barrier layer along the bottom of the via is partially or completely removed, and the via is filled with a conductive material. In another embodiment, a first barrier layer is formed along the bottom and sidewalls of the via. Thereafter, the first barrier layer along the bottom of the via is partially or completely removed, and a second barrier layer is formed.

摘要翻译： 提供具有独特的阻挡层结构的通孔。 在一个实施例中，通孔在通孔中形成阻挡层而形成通孔。 沿着通孔底部的阻挡层被部分地或完全去除，并且通孔用导电材料填充。 在另一个实施例中，沿着通孔的底部和侧壁形成第一阻挡层。 此后，沿通孔底部的第一阻挡层被部分地或完全地去除，形成第二阻挡层。

公开(公告)号：US20050239288A1

公开(公告)日：2005-10-27

申请号：US10910182

申请日：2004-08-02

申请人： Chao-Hsien Peng ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

发明人： Chao-Hsien Peng ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/02046 ,  H01L21/32136 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838

摘要： A method for forming a barrier layer upon a copper containing conductor layer employs a hydrogen containing plasma treatment of the copper containing conductor layer followed by an argon plasma treatment of the copper containing conductor layer. The barrier layer may be formed employing a chemical vapor deposition method, such as an atomic layer deposition method. When the deposition method employs a metal and carbon containing source material, the two-step plasma pretreatment provides the barrier layer with enhanced electrical properties.

摘要翻译： 在含铜导体层上形成阻挡层的方法采用含铜导体层的含氢等离子体处理，然后进行含铜导体层的氩等离子体处理。 可以使用诸如原子层沉积方法的化学气相沉积方法形成阻挡层。 当沉积方法采用含金属和碳的源材料时，两步等离子体预处理为阻挡层提供了增强的电性能。

公开(公告)号：US06949472B1

公开(公告)日：2005-09-27

申请号：US10838720

申请日：2004-05-03

申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC分类号： H01L21/306 ,  H01L21/31 ,  H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/02046 ,  H01L21/76862 ,  H01L21/76865

摘要： A novel method for depositing a barrier layer on a single damascene, dual damascene or other contact opening structure. The method eliminates the need for pre-cleaning argon ion bombardment of the structure, thereby reducing or eliminating damage to the surface of the underlying conductive layer and sputtering of copper particles to the via or other contact opening sidewall. The process includes fabrication of a single damascene, dual damascene or other contact opening structure on a substrate; optionally pre-cleaning the structure typically using nitrogen or hydrogen plasma; depositing a thin metal barrier layer on the sidewalls and bottom of the structure; and redistributing or re-sputtering the barrier layer on the bottom and sidewalls of the structure.

摘要翻译： 一种用于在单个镶嵌，双镶嵌或其他接触开口结构上沉积阻挡层的新方法。 该方法消除了对结构的氩离子轰击的预清洁的需要，从而减少或消除了下面的导电层的表面的损伤和铜颗粒溅射到通孔或其他接触开口侧壁。 该方法包括在基底上制造单个镶嵌，双镶嵌或其它接触开口结构; 可以任选地预先使用氮或氢等离子体对结构进行预清洗; 在结构的侧壁和底部上沉积薄金属阻挡层; 并且在结构的底部和侧壁上重新分布或重新溅射阻挡层。

公开(公告)号：US06815336B1

公开(公告)日：2004-11-09

申请号：US09160965

申请日：1998-09-25

申请人： Shau-Lin Shue ,  Syun-Ming Jang

发明人： Shau-Lin Shue ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/2885 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/7684

摘要： Methods are disclosed to improve the planarization of copper damascene by the steps of patterning on the copper damascene a photoresist using a reverse tone photo mask or a reverse tone photo mask of the metal lines, removing excess copper by reverse current plating or by dry or wet chemical etching, stripping the photo resist, and a subsequent chemical mechanical planarization of the copper damascene. Lastly a cap layer is applied to the planarized surface. In a variant of the disclosed method a more relaxed reverse tone photo mask of the metal lines is used, which may be more desirable for practical use. These steps provide benefits such as improved uniformity of the wafer surface, reduce the dishing of metal lines (trenches) and pads, and reduce oxide erosion.

摘要翻译： 公开了通过以下步骤来改善铜镶嵌的平面化的步骤：使用反色调光掩模或金属线的反色调光掩模在铜镶嵌光致抗蚀剂上进行图案化，通过反向电镀或通过干或湿去除多余的铜 化学蚀刻，剥离光致抗蚀剂，以及铜镶嵌件的随后的化学机械平面化。 最后，将覆盖层施加到平坦化表面。 在所公开的方法的变型中，使用金属线的更宽松的反向色调光掩模，这对于实际使用可能是更理想的。 这些步骤提供了诸如改善晶片表面的均匀性，减少金属线（沟槽）和焊盘的凹陷以及减少氧化物侵蚀的益处。

公开(公告)号：US06797144B2

公开(公告)日：2004-09-28

申请号：US10141277

申请日：2002-05-08

申请人： Hung-Wen Su ,  Shih-Wei Chou ,  Ching-Hua Hsieh ,  Shau-Lin Shue

发明人： Hung-Wen Su ,  Shih-Wei Chou ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC分类号： C25D712

CPC分类号： H01L21/2885 ,  C25D7/123 ,  H01L21/76877

摘要： A method for in-situ cleaning an electrodeposition surface following an electroplating process including providing a first electrode assembly and a second electrode assembly; applying a first current density across the first electrode assembly and the second electrode assembly for carrying out the electrodeposition process; carrying out the electrodeposition process to electrodeposit a metal onto an electrodeposition surface of the second electrode assembly; and, applying a second current density having a second polarity reversed with reference to the first polarity across the first electrode assembly and the second electrode assembly the second current density having a relatively lower current density compared to the first current density.

摘要翻译： 一种用于在电镀工艺之后原位清洁电沉积表面的方法，包括提供第一电极组件和第二电极组件; 在第一电极组件和第二电极组件上施加第一电流密度以执行电沉积过程; 执行电沉积工艺以将金属电沉积到第二电极组件的电沉积表面上; 并且相对于第一电流密度，第二电流密度具有相对于第一极性反转的第二电流密度跨越第一电极组件和第二电极组件，第二电流密度具有相对较低的电流密度。

公开(公告)号：US06737352B2

公开(公告)日：2004-05-18

申请号：US10194630

申请日：2002-07-12

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Ya

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Ya

IPC分类号： H01L214763

CPC分类号： H01L21/76802

摘要： A method to prevent particle generation from sputtering clean is disclosed, the method comprises of forming a dielectric layer on a substrate, forming a nitrogen-containing dielectric layer on the dielectric layer, forming a plurality of contact holes in the dielectric layer and the nitrogen-containing dielectric layer, coating a sacrificial layer into the contact holes and on the nitrogen-containing dielectric layer, removing the sacrificial layer and the nitrogen-containing dielectric layer on top of the dielectric layer, removing said sacrificial layer in said contact holes and performing an argon sputtering clean.

摘要翻译： 公开了一种防止溅射清洁产生颗粒的方法，该方法包括在基板上形成电介质层，在电介质层上形成含氮介电层，在电介质层中形成多个接触孔， 在所述接触孔和所述含氮电介质层上涂覆牺牲层，在所述电介质层的顶部上去除所述牺牲层和所述含氮介电层，去除所述接触孔中的所述牺牲层，并执行 氩气溅射清洗。