公开(公告)号：US20070181434A1

公开(公告)日：2007-08-09

申请号：US11783245

申请日：2007-04-06

Applicant: Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

Inventor： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC: C25D5/34 ,  H01L21/44 ,  C25D3/38

CPC classification number: H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

Abstract translation: 电化学沉积（ECD）的方法在衬底上提供阻挡层和种子层。 在将金属层电化学沉积在具有物理或化学表面处理工艺的电化学镀覆电池中之前，对基板的表面进行预处理。 电化学镀覆电池被盖覆盖以防止电解质溶液的蒸发。 电化学电镀单元包括具有提升密封件的衬底保持器组件，例如在提升密封件和衬底之间的接触角θ小于90°。 衬底保持器组件包括在衬底的后侧的衬底卡盘。

公开(公告)号：US20060099802A1

公开(公告)日：2006-05-11

申请号：US10985149

申请日：2004-11-10

Applicant: Jing-Cheng Lin ,  Shau-Lin Shue

Inventor： Jing-Cheng Lin ,  Shau-Lin Shue

IPC: H01L21/4763

CPC classification number: H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

Abstract: A semiconductor structure having a via formed in a dielectric layer is provided. The exposed pores of the dielectric material along the sidewalls of the via are partially or completely sealed. Thereafter, one or more barrier layers may be formed and the via may be filled with a conductive material. The barrier layers formed over the sealing layer exhibits a more continuous barrier layer. The pores may be partially or completely sealed by performing, for example, a plasma process in an argon environment.

Abstract translation: 提供了具有形成在电介质层中的通孔的半导体结构。 沿着通孔的侧壁的电介质材料的暴露的孔部分或完全密封。 此后，可以形成一个或多个阻挡层，并且可以用导电材料填充通孔。 形成在密封层之上的阻挡层表现出更连续的阻挡层。 通过在氩气环境中进行例如等离子体处理，可以将孔部分或完全密封。

公开(公告)号：US20050266679A1

公开(公告)日：2005-12-01

申请号：US10995752

申请日：2004-11-23

Applicant: Jing-Cheng Lin ,  Shau-Lin Shue

Inventor： Jing-Cheng Lin ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/4763 ,  H01L23/52

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76865

Abstract: A via having a unique barrier layer structure is provided. In an embodiment, a via is formed by forming a barrier layer in a via. The barrier layer along the bottom of the via is partially or completely removed, and the via is filled with a conductive material. In another embodiment, a first barrier layer is formed along the bottom and sidewalls of the via. Thereafter, the first barrier layer along the bottom of the via is partially or completely removed, and a second barrier layer is formed.

Abstract translation: 提供具有独特的阻挡层结构的通孔。 在一个实施例中，通孔在通孔中形成阻挡层而形成通孔。 沿着通孔底部的阻挡层被部分地或完全去除，并且通孔用导电材料填充。 在另一个实施例中，沿着通孔的底部和侧壁形成第一阻挡层。 此后，沿通孔底部的第一阻挡层被部分地或完全地去除，形成第二阻挡层。

公开(公告)号：US20050239288A1

公开(公告)日：2005-10-27

申请号：US10910182

申请日：2004-08-02

Applicant: Chao-Hsien Peng ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Chao-Hsien Peng ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/02046 ,  H01L21/32136 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838

Abstract: A method for forming a barrier layer upon a copper containing conductor layer employs a hydrogen containing plasma treatment of the copper containing conductor layer followed by an argon plasma treatment of the copper containing conductor layer. The barrier layer may be formed employing a chemical vapor deposition method, such as an atomic layer deposition method. When the deposition method employs a metal and carbon containing source material, the two-step plasma pretreatment provides the barrier layer with enhanced electrical properties.

Abstract translation: 在含铜导体层上形成阻挡层的方法采用含铜导体层的含氢等离子体处理，然后进行含铜导体层的氩等离子体处理。 可以使用诸如原子层沉积方法的化学气相沉积方法形成阻挡层。 当沉积方法采用含金属和碳的源材料时，两步等离子体预处理为阻挡层提供了增强的电性能。

公开(公告)号：US20050170648A1

公开(公告)日：2005-08-04

申请号：US11056758

申请日：2005-02-11

Applicant: Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

Abstract: A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

公开(公告)号：US06551915B2

公开(公告)日：2003-04-22

申请号：US09898980

申请日：2001-07-03

Applicant: Jing-Cheng Lin ,  Shau-Lin Shue

Inventor： Jing-Cheng Lin ,  Shau-Lin Shue

IPC: H01L2144

CPC classification number: H01L21/76828 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76826

Abstract: Within a damascene method for forming a patterned conductor layer within an aperture defined by a patterned dielectric layer within a microelectronic fabrication, at least one of: (1) the patterned dielectric layer is thermally annealed at a temperature of from about 300 to about 450 degrees centigrade prior to forming within the aperture the patterned conductor layer; and (2) the aperture is etched with a plasma employing an etchant gas composition comprising hydrogen to form a laterally enlarged aperture prior to forming within the laterally enlarged aperture the patterned conductor layer. In accord with the method, the microelectronic fabrication is formed with decreased contact resistance and enhanced structural integrity.

公开(公告)号：US07443029B2

公开(公告)日：2008-10-28

申请号：US11201845

申请日：2005-08-11

Applicant: Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

Abstract translation: 提供了一种新的方法和结构，用于创建铜双镶嵌互连。 在电介质层中产生双镶嵌结构，任选地，金属阻挡层沉积在双镶嵌结构的暴露表面上。 沉积铜籽晶层，双镶嵌结构填充铜。 对所制造的铜互连进行退火，之后从电介质去除多余的铜。 对本发明至关重要的是，然后在铜双镶嵌互连件上沉积薄层的氧化物作为覆盖层，然后将蚀刻停止层沉积在氧化物薄层上用于持续的上层金属化。

公开(公告)号：US20060027922A1

公开(公告)日：2006-02-09

申请号：US10909980

申请日：2004-08-03

Applicant: Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Cheng-Lin Huang ,  Li-Lin Su ,  Shau-Lin Shue

Inventor： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Cheng-Lin Huang ,  Li-Lin Su ,  Shau-Lin Shue

IPC: H01L23/48

CPC classification number: H01L21/76834 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.

Abstract translation: 一种具有包括第一金属元件的非导电盖层的半导体器件。 非导电盖层包括导电线上的第一金属氮化物，第一金属氧化物或第一金属氧氮化物，以及导电线之间的绝缘材料。 界面区域可以形成在导电线的顶表面上，界面区域包括盖层的金属元件。 盖层防止导电线中的导电材料迁移或扩散到相邻的随后形成的绝缘材料层中。 盖层也可以用作蚀刻停止层。

公开(公告)号：US20050054202A1

公开(公告)日：2005-03-10

申请号：US10655972

申请日：2003-09-04

Applicant: Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

Inventor： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

IPC: H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/3105 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76873

Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

Abstract translation: 一种用于形成铜镶嵌特征的方法，包括提供半导体工艺晶片，其包括形成为延伸穿过至少一个介电绝缘层的厚度的至少一个通孔开口，以及覆盖所述至少一个通孔开口的上覆沟槽开口，以形成双重 大马士革开幕 在所述至少一个通孔开口底部处蚀刻通过蚀刻停止层以暴露下面的铜区域; 在含氢环境中同时加热工艺晶片，进行亚低温DEGAS工艺; 进行原位溅射清洗过程; 并且原位形成阻挡层以使双镶嵌开口成线。

公开(公告)号：US07338903B2

公开(公告)日：2008-03-04

申请号：US10910182

申请日：2004-08-02

Applicant: Chao-Hsien Peng ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Chao-Hsien Peng ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/44

CPC classification number: H01L21/76831 ,  H01L21/02046 ,  H01L21/32136 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838

Abstract: A method for forming a barrier layer upon a copper containing conductor layer employs a hydrogen containing plasma treatment of the copper containing conductor layer followed by an argon plasma treatment of the copper containing conductor layer. The barrier layer may be formed employing a chemical vapor deposition method, such as an atomic layer deposition method. When the deposition method employs a metal and carbon containing source material, the two-step plasma pretreatment provides the barrier layer with enhanced electrical properties.

Abstract translation: 在含铜导体层上形成阻挡层的方法采用含铜导体层的含氢等离子体处理，然后进行含铜导体层的氩等离子体处理。 可以使用诸如原子层沉积方法的化学气相沉积方法形成阻挡层。 当沉积方法采用含金属和碳的源材料时，两步等离子体预处理为阻挡层提供了增强的电性能。