公开(公告)号：US07443005B2

公开(公告)日：2008-10-28

申请号：US10982978

申请日：2004-11-05

申请人： Ching-Sen Kuo ,  Feng-Jia Shiu ,  Gwo-Yuh Shiau ,  Jieh-Jang Chen ,  Shih-Chi Fu ,  Chien Hsien Tseng ,  Chia-Shiung Tsai ,  Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chih-Ta Wu ,  Chi-Hsin Lo

发明人： Ching-Sen Kuo ,  Feng-Jia Shiu ,  Gwo-Yuh Shiau ,  Jieh-Jang Chen ,  Shih-Chi Fu ,  Chien Hsien Tseng ,  Chia-Shiung Tsai ,  Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chih-Ta Wu ,  Chi-Hsin Lo

IPC分类号： H01L29/78

CPC分类号： H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687

摘要： An image sensor includes a double-microlens structure with an outer microlens aligned over an inner microlens, both microlenses aligned over a corresponding photosensor. The inner or outer microlens may be formed by a silylation process in which a reactive portion of a photoresist material reacts with a silicon-containing agent. The inner or outer microlens may be formed by step etching of a dielectric material, the step etching process including a series of alternating etch steps including an anisotropic etching step and an etching step that causes patterned photoresist to laterally recede. Subsequent isotropic etching processes may be used to smooth the etched step structure and form a smooth lens. A thermally stable and photosensitive polymeric/organic material may also be used to form permanent inner or outer lenses. The photosensitive material is coated then patterned using photolithography, reflowed, then cured to form a permanent lens structure.

摘要翻译： 图像传感器包括双微透镜结构，其外部微透镜在内部微透镜上对准，两个微透镜在相应的光电传感器上对准。 内部或外部微透镜可以通过甲硅烷基化方法形成，其中光致抗蚀剂材料的反应性部分与含硅试剂反应。 内部或外部微透镜可以通过介电材料的步骤蚀刻形成，该步骤蚀刻工艺包括一系列交替蚀刻步骤，其包括各向异性蚀刻步骤和使图案化光致抗蚀剂横向后退的蚀刻步骤。 可以使用随后的各向同性蚀刻工艺来平滑蚀刻的台阶结构并形成光滑的透镜。 热稳定和感光的聚合物/有机材料也可用于形成永久的内镜片或外镜片。 感光材料被涂覆，然后使用光刻图案化，回流，然后固化以形成永久性透镜结构。

公开(公告)号：US07906418B2

公开(公告)日：2011-03-15

申请号：US10727272

申请日：2003-12-03

申请人： Chung-Yi Yu ,  Chi-Hsin Lo ,  Chia Shiung Tsai

发明人： Chung-Yi Yu ,  Chi-Hsin Lo ,  Chia Shiung Tsai

IPC分类号： H01L21/3205

CPC分类号： H01L27/11521 ,  H01L23/485 ,  H01L27/115 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device, wherein a gate structure is formed over a substrate, an interconnect layer is formed over the gate structure and the substrate, and a cap layer is formed over the interconnect layer. The interconnect layer and the cap layer are then planarized to form a substantially planar surface. A mask layer, such as an oxide mask layer, is formed over the planarized portions of the interconnect layer, and the planarized cap layer and portions of the interconnect layer are removed by etching around the mask layer.

摘要翻译： 一种制造半导体器件的方法，其中在衬底上形成栅极结构，在所述栅极结构和所述衬底之上形成互连层，并且在所述互连层上形成覆盖层。 然后将互连层和覆盖层平坦化以形成基本平坦的表面。 在互连层的平坦化部分上形成掩模层，例如氧化物掩模层，并且通过围绕掩模层进行蚀刻来去除平坦化的覆盖层和互连层的部分。

公开(公告)号：US07586145B2

公开(公告)日：2009-09-08

申请号：US11191437

申请日：2005-07-27

申请人： Yuan-Hung Liu ,  Shih-Chi Fu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Shih-Chi Fu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

摘要： An EEPROM flash memory device having a floating gate electrode enabling a reduced erase voltage and method for forming the same, the floating gate electrode including an outer edge portion including multiple charge transfer pointed tips.

摘要翻译： 一种具有能够减小擦除电压的浮动栅电极的EEPROM闪速存储器件及其形成方法，该浮栅电极包括包括多个电荷转移尖端的外边缘部分。

公开(公告)号：US20080246152A1

公开(公告)日：2008-10-09

申请号：US11696296

申请日：2007-04-04

申请人： Ming-Chyi Liu ,  Yuan-Hung Liu ,  Gwo-Yuh Shiau ,  Yuan-Chih Hsieh ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Ming-Chyi Liu ,  Yuan-Hung Liu ,  Gwo-Yuh Shiau ,  Yuan-Chih Hsieh ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/14636 ,  H01L27/14643 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45166 ,  H01L2224/4807 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48505 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/45124 ,  H01L2224/05655 ,  H01L2924/00

摘要： A semiconductor device with a bonding pad is provided. The semiconductor device includes a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are disposed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is disposed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad, and the first substrate is exposed through an opening in the lowermost metal pattern.

摘要翻译： 提供具有接合焊盘的半导体器件。 半导体器件包括具有器件面积和接合面积的第一衬底，其中第一衬底具有上表面和底表面。 半导体元件设置在器件区域中的第一衬底的上表面上。 在接合区域中的第一金属间介电层设置在基板的上表面上。 最下面的金属图案设置在第一金属间介质层中，其中最下面的金属图形用作接合焊盘，第一基板通过最下面的金属图案中的开口露出。

公开(公告)号：US07202130B2

公开(公告)日：2007-04-10

申请号：US10775290

申请日：2004-02-10

申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A spacer, a split gate flash memory cell, and related method of forming the same. In one aspect, a composite spacer includes a first spacer insulating layer having a first deposition distribution that varies as a function of a location on a substrate. The composite spacer also includes a second spacer insulating layer having a second deposition distribution that varies in substantial opposition to the first deposition distribution. In another aspect, a composite spacer includes a first spacer insulating layer having a substantially uniform deposition distribution across a surface thereof. The composite spacer also includes a second spacer insulating layer having a varying deposition distribution with a thinner composition in selected regions of the memory cell. In another aspect, a coupling spacer provides for a conductive layer that extends between a floating gate and a substrate insulating layer adjacent a source recessed into the substrate of the memory cell.

摘要翻译： 间隔物，分裂栅极闪存单元及其相关方法。 在一个方面，一种复合间隔物包括具有第一沉积分布的第一间隔绝缘层，其随着基底上的位置而变化。 复合间隔物还包括具有与第一沉积分布基本相反的第二沉积分布的第二间隔绝缘层。 在另一方面，复合间隔物包括在其表面上具有基本均匀的沉积分布的第一间隔绝缘层。 复合间隔物还包括具有在存储单元的选定区域中具有较薄组成的不同沉积分布的第二间隔绝缘层。 在另一方面，耦合间隔物提供导电层，该导电层在浮置栅极和与凹入到存储器单元的衬底中的源极相邻的衬底绝缘层之间延伸。

公开(公告)号：US20070287247A1

公开(公告)日：2007-12-13

申请号：US11422701

申请日：2006-06-07

申请人： Ming-Chyi Liu ,  Chi-Hsin Lo

发明人： Ming-Chyi Liu ,  Chi-Hsin Lo

IPC分类号： H01L21/8244

CPC分类号： H01L28/60 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L27/10852 ,  H01L27/10855

摘要： A semiconductor device with an embedded capacitor structure. A dielectric layer is disposed on a substrate, having a contact opening exposing the substrate and a trench opening above the contact opening. A first metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A second metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A capacitor dielectric layer is interposed between the first and second metal electrode layers. A method for fabricating the semiconductor device is also disclosed.

摘要翻译： 具有嵌入式电容器结构的半导体器件。 介电层设置在基板上，具有暴露基板的接触开口和接触开口上方的沟槽开口。 第一金属电极层共形地设置在触点和沟槽开口的侧壁和底部之上。 第二金属电极层共形地设置在触点和沟槽开口的侧壁和底部之上。 电容器电介质层介于第一和第二金属电极层之间。 还公开了制造半导体器件的方法。

公开(公告)号：US6003526A

公开(公告)日：1999-12-21

申请号：US928950

申请日：1997-09-12

申请人： Chi-Hsin Lo ,  Hsing-Yuan Cheu

发明人： Chi-Hsin Lo ,  Hsing-Yuan Cheu

IPC分类号： H01J37/32 ,  H01L21/00 ,  B08B5/00

CPC分类号： H01L21/67028 ,  H01J37/32862

摘要： A method for cleaning a plasma etch chamber is described which can be carried out by first terminating an etch process by stopping a process gas flow into the chamber, then maintaining a RF power in the etch chamber, and flowing a cleaning gas consists of at least one inert gas and oxygen through the chamber at a flow rate higher than the flow rate for the process gas for a length of time sufficient to evacuate substantially all the contaminating byproducts formed by the process gas. A suitable cleaning gas contains at least one inert gas of Ar, He, or N.sub.2 mixed with O.sub.2. A sufficient length of time for the cleaning process is at least 5 seconds, and preferably at least 10 seconds.

摘要翻译： 描述了用于清洁等离子体蚀刻室的方法，其可以通过首先通过停止工艺气体流入室中终止蚀刻工艺，然后在蚀刻室中保持RF功率，并且清洁气体的流动至少由 一个惰性气体和氧气通过腔室，流速高于处理气体的流速足以将基本上所有由工艺气体形成的污染副产物抽空的时间。 合适的清洁气体含有与O2混合的至少一种Ar，He或N 2的惰性气体。 清洁过程的足够长的时间是至少5秒，优选至少10秒。

公开(公告)号：US5755891A

公开(公告)日：1998-05-26

申请号：US789214

申请日：1997-01-24

申请人： Chi-Hsin Lo ,  Dowson Jang ,  Hsueh-Liang Chiu

发明人： Chi-Hsin Lo ,  Dowson Jang ,  Hsueh-Liang Chiu

IPC分类号： B08B7/00 ,  B08B6/00 ,  H01L21/302

CPC分类号： B08B7/0035

摘要： An improved process is described for the post-etching treatment after subtractive etching of aluminum and aluminum-alloy layers in the fabrication of semiconductor integrated circuit devices. The improvement consists of in situ exposure immediately after subtractive etching of the metal pattern to a reactive plasma sustained in a mixture of oxygen and carbon tetrafluoride gases by continuous radiofrequency power input for a controlled period of time.

摘要翻译： 对在半导体集成电路器件的制造中对铝和铝合金层进行减蚀蚀后的后蚀刻处理进行了描述。 该改进包括在通过连续的射频功率输入在受控时间段内将金属图案减去蚀刻到氧气和四氟化碳气体的混合物中的反应性等离子体之后立即曝光。

公开(公告)号：US08188527B2

公开(公告)日：2012-05-29

申请号：US11422701

申请日：2006-06-07

申请人： Ming-Chyi Liu ,  Chi-Hsin Lo

发明人： Ming-Chyi Liu ,  Chi-Hsin Lo

IPC分类号： H01L27/108

CPC分类号： H01L28/60 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L27/10852 ,  H01L27/10855

摘要： A semiconductor device with an embedded capacitor structure. A dielectric layer is disposed on a substrate, having a contact opening exposing the substrate and a trench opening above the contact opening. A first metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A second metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A capacitor dielectric layer is interposed between the first and second metal electrode layers. A method for fabricating the semiconductor device is also disclosed.

摘要翻译： 具有嵌入式电容器结构的半导体器件。 介电层设置在基板上，具有暴露基板的接触开口和接触开口上方的沟槽开口。 第一金属电极层共形地设置在触点和沟槽开口的侧壁和底部之上。 第二金属电极层共形地设置在触点和沟槽开口的侧壁和底部之上。 电容器电介质层介于第一和第二金属电极层之间。 还公开了制造半导体器件的方法。

公开(公告)号：US20100301303A1

公开(公告)日：2010-12-02

申请号：US12713541

申请日：2010-02-26

申请人： Ming-Tsong Wang ,  Chien-Chih Chiu ,  Tsun Kai Tsao ,  Chi-Hsin Lo

发明人： Ming-Tsong Wang ,  Chien-Chih Chiu ,  Tsun Kai Tsao ,  Chi-Hsin Lo

IPC分类号： H01L45/00 ,  H01L21/8239 ,  H01L27/105

CPC分类号： H01L27/2436 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/145

摘要： An integrated circuit structure includes a dielectric layer having an upper portion and a lower portion. The dielectric layer is either an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD). A phase change random access memory (PCRAM) cell includes a phase change strip, wherein the phase change strip is on the lower portion and has a top surface lower than a top surface of the dielectric layer, and a bottom surface higher than a bottom surface of the dielectric layer. A first conductive column is electrically connected to the phase change strip. The first conductive column extends from the top surface of the dielectric layer down into the dielectric layer. A second conductive column is in a peripheral region. The second conductive column extends from the top surface of the dielectric layer down into the dielectric layer. The first conductive column and the second conductive column have different heights.

摘要翻译： 集成电路结构包括具有上部和下部的电介质层。 电介质层是层间电介质（ILD）或金属间电介质（IMD）。 相变随机存取存储器（PCRAM）单元包括相变带，其中相变带位于下部并具有比电介质层的顶表面低的顶表面，并且底表面高于底表面 的介电层。 第一导电柱电连接到相变带。 第一导电柱从电介质层的顶表面延伸到介电层中。 第二导电柱位于周边区域中。 第二导电柱从电介质层的顶表面延伸到介电层中。 第一导电柱和第二导电柱具有不同的高度。