公开(公告)号：US20200242461A1

公开(公告)日：2020-07-30

申请号：US16360955

申请日：2019-03-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly

IPC: G06N3/063 ,  G11C11/54 ,  G11C11/4063 ,  G06F12/0811

Abstract: Various algorithms are disclosed for verifying the stored weight in a non-volatile memory cell in a neural network following a multilevel programming operation of the non-volatile memory cell by converting the stored weight into a plurality of digital output bits. Circuity, such as an adjustable reference current source, for implementing the algorithms are disclosed.

公开(公告)号：US12237011B2

公开(公告)日：2025-02-25

申请号：US17853315

申请日：2022-06-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Han Tran ,  Kha Nguyen ,  Hien Pham

IPC: G11C11/56 ,  G06F17/16 ,  G06N3/06 ,  G11C11/16 ,  G11C11/4074

Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.

公开(公告)号：US20240265951A1

公开(公告)日：2024-08-08

申请号：US18137370

申请日：2023-04-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hoa Vu ,  Stephen Trinh ,  Stanley Hong ,  Thuan Vu ,  Nghia Le ,  Duc Nguyen ,  Hien Pham

IPC: G11C5/14 ,  G11C7/02 ,  G11C13/00

CPC classification number: G11C5/147 ,  G11C7/02 ,  G11C13/004

Abstract: In one example, a system comprises a current-to-voltage converter to generate differential voltages from differential currents comprising a first current and a second current, the current-to-voltage converter comprising: a first bitline to provide the first current; a second bitline to provide the second current; a first regulator to apply a first voltage to the first bitline; a second regulator to apply a second voltage to the second bitline; a regulating circuit comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first output terminal and the second output terminal providing the differential voltages; and a common mode circuit.

公开(公告)号：US20240256846A1

公开(公告)日：2024-08-01

申请号：US18135664

申请日：2023-04-17

Applicant: Silicon Storage Technology, Inc

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC: G06N3/065

CPC classification number: G06N3/065

Abstract: Numerous examples are disclosed of multiplexors coupled to rows in a neural network array. In one example, a system comprises a neural network array of non-volatile memory cells comprising i rows, where i is a multiple of 2; j row registers, where j

公开(公告)号：US20240256146A1

公开(公告)日：2024-08-01

申请号：US18134928

申请日：2023-04-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Kha Nguyen ,  Stephen Trinh ,  Stanley Hong ,  Hien Pham

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Numerous examples are disclosed of systems and methods to implement redundancy. In one example, a system comprises an array of non-volatile memory cells; a redundant array of non-volatile memory cells; and an input block coupled to respective rows in the array and respective rows in the redundant array and comprising row tag registers and redundant row tag registers.

公开(公告)号：US20240098991A1

公开(公告)日：2024-03-21

申请号：US18520526

申请日：2023-11-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Toan Le ,  Nghia Le ,  Hien Pham

IPC: H10B41/42 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

CPC classification number: H10B41/42 ,  G06N3/08 ,  G11C16/0425 ,  H01L29/7883

Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

公开(公告)号：US11915747B2

公开(公告)日：2024-02-27

申请号：US17856839

申请日：2022-07-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G06N3/065

CPC classification number: G11C11/54 ,  G06N3/065 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C2216/04

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

公开(公告)号：US20230325649A1

公开(公告)日：2023-10-12

申请号：US17847486

申请日：2022-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Mark Reiten

IPC: G06N3/063 ,  G06F17/16

CPC classification number: G06N3/0635 ,  G06F17/16

Abstract: Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog inputs. In one example, a system comprises a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, a capacitor comprising a first terminal and a second terminal, the second terminal coupled to a common potential, a row decoder to enable an application of an input signal to the first terminal of the capacitor in response to an address, and a buffer coupled to the first terminal of the capacitor, the buffer to generate an output voltage for a respective row of the vector by matrix multiplication array.

公开(公告)号：US20230178147A1

公开(公告)日：2023-06-08

申请号：US18103383

申请日：2023-01-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari

IPC: G11C11/54 ,  G11C16/04 ,  G06N3/063 ,  G11C16/26 ,  G11C16/28 ,  H03F3/00 ,  H03M1/16 ,  G06N3/065

CPC classification number: G11C11/54 ,  G11C16/0425 ,  G06N3/063 ,  G11C16/26 ,  G11C16/0416 ,  G11C16/28 ,  H03F3/005 ,  H03M1/164 ,  G06N3/065 ,  H03M1/38

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).

公开(公告)号：US11532354B2

公开(公告)日：2022-12-20

申请号：US17024410

申请日：2020-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063 ,  G11C16/10

Abstract: Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.