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    Circuit arrangement for generating an n-bit output pointer, semiconductor memory and method for adjusting a read latency
    42.
    发明授权
    Circuit arrangement for generating an n-bit output pointer, semiconductor memory and method for adjusting a read latency 失效
    用于产生n位输出指针的电路装置，半导体存储器和用于调整读延迟的方法

    公开(公告)号：US07428184B2

    公开(公告)日：2008-09-23

    申请号：US11593234

    申请日：2006-11-06

    申请人： Stefan Dietrich

    发明人： Stefan Dietrich

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  G06F5/10 ,  G11C7/222

    摘要： A circuit arrangement for generating an n-bit output pointer in a semiconductor memory comprises at least one m-bit interface for accepting an m-bit reference signal, at least one m-bit binary counter, a decoder arrangement connected downstream of the binary counter, and outputs for providing the bits of the output pointer. The reference signal comprises an information regarding a read latency to be adjusted utilizing the output pointer, the at least one counter provides an m-bit counter reading signal comprising a current counter reading, and the decoder arrangement comprises a plurality of decoder devices each comparing the current counter reading signal with a reference value which is associated with a respective of the decoder devices. Each decoder device provides one bit of the output pointer on the basis of the comparing.

    摘要翻译： 用于在半导体存储器中产生n位输出指针的电路装置包括至少一个用于接受m位参考信号的m位接口，至少一个m位二进制计数器，连接在二进制计数器下游的解码器装置 ，以及用于提供输出指针的位的输出。 所述参考信号包括关于使用所述输出指针进行调整的读等待时间的信息，所述至少一个计数器提供包括当前计数器读数的m位计数器读取信号，并且所述解码器装置包括多个解码器装置， 具有与各个解码器装置相关联的参考值的当前计数器读取信号。 每个解码器装置在比较的基础上提供一位输出指针。

    Memory including a write training block
    43.
    发明授权
    Memory including a write training block 有权
    内存包括一个写入训练块

    公开(公告)号：US07415569B2

    公开(公告)日：2008-08-19

    申请号：US11386360

    申请日：2006-03-22

    申请人： Stefan Dietrich ,  Rex Kho

    发明人： Stefan Dietrich ,  Rex Kho

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1078 ,  G11C7/1087 ,  G11C7/1093

    摘要： A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter and a write training block. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for moving the FIFO output pointer based on data read from the FIFO cells.

    摘要翻译： 存储器包括多个先进先出（FIFO）单元，输出指针计数器和写入训练块。 输出指针计数器用于切换FIFO单元格中FIFO输出指针的值。 写入训练块用于根据从FIFO单元读取的数据产生用于移动FIFO输出指针的信息。

    Circuit for data bit inversion
    44.
    发明授权
    Circuit for data bit inversion 有权
    数据位反转电路

    公开(公告)号：US07405981B2

    公开(公告)日：2008-07-29

    申请号：US11372738

    申请日：2006-03-10

    申请人： Stefan Dietrich

    发明人： Stefan Dietrich

    IPC分类号： G11C7/10

    CPC分类号： G06F11/08 ,  G11C7/1006

    摘要： An electric circuit for inverting a data bit of a data burst read out from a memory module comprises a buffer for buffering a data burst being comprised of at least two data words, a decoder device comprised of at least two parallel-connected decoders, each comparing bitwise and simultaneously two neighbouring data words of the data words buffered in the buffer and generating an inversion flag, if the number of different data bits of the two neighbouring data words exceeds half the number of data bits of a data word, a correction device for generating a corrected inversion flag for a specific decoder of the decoders by inverting or not inverting the inversion flag of the specific decoder dependent on the inversion flag generated by the specific decoder and the inversion flags generated by the remaining of the decoders, and an inversion device comprised of a plurality of inverters, each inverting or not inverting a present of the data words of an associated of the decoders dependent on the corrected inversion flag of the associated decoder.

    摘要翻译： 用于反相从存储器模块读出的数据脉冲串的数据位的电路包括用于缓冲由至少两个数据字组成的数据脉冲串的缓冲器，由至少两个并联连接的解码器组成的解码器装置，每个比较 如果两个相邻数据字的不同数据位的数量超过数据字的数据位的数量的一半，则缓冲器中缓冲的数据字的两个相邻的数据字并且产生反转标志，校正装置 通过根据由特定解码器产生的反转标志和由剩余的解码器产生的反转标志反转或不反转特定解码器的反转标志来产生解码器的特定解码器的校正反转标志，以及反转装置 由多个反相器组成，每个逆变器反相或不反转依赖于解码器的相关联的数据字的存在 相关解码器的校正反转标志。

    Filtering bit position in a memory
    45.
    发明申请
    Filtering bit position in a memory 失效
    在存储器中过滤位位置

    公开(公告)号：US20070226430A1

    公开(公告)日：2007-09-27

    申请号：US11386377

    申请日：2006-03-22

    申请人： Stefan Dietrich

    发明人： Stefan Dietrich

    IPC分类号： G06F13/00

    CPC分类号： G11C7/1078 ,  G06F5/10 ,  G11C7/04 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/406 ,  G11C11/40615 ,  G11C19/287 ,  G11C2207/005

    摘要： A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a temporary data register. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for moving the FIFO output pointer based on data read from the FIFO cells. The temporary data register is for storing a single bit representing one or more bits in each FIFO cell.

    摘要翻译： 存储器包括多个先进先出（FIFO）单元，输出指针计数器，写入训练块和临时数据寄存器。 输出指针计数器用于切换FIFO单元格中FIFO输出指针的值。 写入训练块用于根据从FIFO单元读取的数据移动FIFO输出指针。 临时数据寄存器用于存储表示每个FIFO单元中的一个或多个位的单个位。

    Day and night film
    46.
    发明申请
    Day and night film 有权
    昼夜电影

    公开(公告)号：US20070133095A1

    公开(公告)日：2007-06-14

    申请号：US11297615

    申请日：2005-12-08

    申请人： Kay-Uwe Schenke ,  Guido Hitschmarin ,  Stefan Dietrich ,  Robert Bennett ,  Paul Humpal ,  Keith Kotchick

    发明人： Kay-Uwe Schenke ,  Guido Hitschmarin ,  Stefan Dietrich ,  Robert Bennett ,  Paul Humpal ,  Keith Kotchick

    IPC分类号： G02B27/00

    CPC分类号： G02B5/0278 ,  G02B5/0236 ,  G02F1/133555

    摘要： An optical element having a front side and a back side operates in an ambient lit mode and a backlit mode. The optical element includes a diffusely reflecting layer facing the front side for reflecting ambient light. A light absorbing layer faces the back side and is positioned to prevent back light from illuminating the diffusely reflecting layer. A plurality of light transmitting regions extend through the light absorbing layer and the diffusely reflecting layer for permitting back light to pass through in a restricted angular range without illuminating the diffusely reflecting layer.

    摘要翻译： 具有前侧和后侧的光学元件在环境照明模式和背光模式下操作。 光学元件包括面向前侧的漫反射层，用于反射环境光。 光吸收层面向背面并被定位成防止背光照射漫反射层。 多个透光区域延伸穿过光吸收层和漫反射层，以允许背光在受限的角度范围内通过而不照射漫反射层。

    Operating method for a laser machining system
    47.
    发明授权
    Operating method for a laser machining system 失效
    激光加工系统的操作方法

    公开(公告)号：US07005604B2

    公开(公告)日：2006-02-28

    申请号：US10933250

    申请日：2004-09-03

    申请人： Stefan Dietrich ,  Johannes Schuchart

    发明人： Stefan Dietrich ,  Johannes Schuchart

    IPC分类号： B23K26/36 ,  B23K26/38

    CPC分类号： H05K3/0038 ,  B23K26/0604 ,  B23K26/382 ,  B23K26/389 ,  B23K26/40 ,  B23K2101/35 ,  B23K2101/42 ,  B23K2103/12 ,  B23K2103/172 ,  B23K2103/50 ,  B23Q7/1442 ,  H05K3/0026 ,  H05K2203/108

    摘要： The invention relates to an operating method and a trolley for a system used for machining objects by using laser beams, particularly for a system used for boring or structuring substrates. The system has a great number of slow-working laser machining machines than rapid working laser machining machines. A rapid-working laser machining machine utilized afterwards or beforehand can be better used to capacity due to the parallel operation of a number of slow-working laser machining machines. The transfer of objects to be machined or already machined objects is preferably effected by means of trolleys, which are both compatible with both the loading stations and the unloading stations of the laser machining machines. This enables the objects, which are to be machined, to be directly received by a trolley located in a loading station and, after machining, to be placed in a trolley that is introduced into an unloading station of a laser machining machine.

    摘要翻译： 本发明涉及一种用于通过使用激光束来加工物体的系统的操作方法和手推车，特别是涉及用于钻孔或构造衬底的系统。 该系统具有大量的快速加工激光加工机器的慢速激光加工机。 由于多台慢速加工的激光加工机器的并联运行，以后或以前使用的快速激光加工机可以更好地用于容量。 被加工物体或已经加工的物体的传送优选地通过手推车来实现，所述手推车既兼容激光加工机器的装载站和卸载站。 这使得被加工的物体能够被位于加载站中的小车直接接收，并且在加工之后被放置在引入到激光加工机的卸载站中的手推车中。

    Memory including an output pointer circuit
    50.
    发明授权
    Memory including an output pointer circuit 有权
    存储器包括一个输出指针电路

    公开(公告)号：US07565466B2

    公开(公告)日：2009-07-21

    申请号：US11386510

    申请日：2006-03-22

    申请人： Stefan Dietrich

    发明人： Stefan Dietrich

    IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F11/00

    CPC分类号： G11C7/1051 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1087

    摘要： A memory including an input register, an input pointer circuit, and an output pointer circuit. The input register is configured to receive and latch-in valid and invalid data via an input pointer and to output the valid data via an output pointer. The input pointer circuit is configured to provide the input pointer based on a continuously running write data strobe clock signal. The output pointer circuit is configured to provide the output pointer based on an external clock signal and to update the output pointer to point to the valid data in the input register based on a write signal.

    摘要翻译： 包括输入寄存器，输入指针电路和输出指针电路的存储器。 输入寄存器被配置为通过输入指针接收和锁存有效和无效数据，并通过输出指针输出有效数据。 输入指针电路被配置为基于连续运行的写数据选通时钟信号来提供输入指针。 输出指针电路被配置为基于外部时钟信号提供输出指针，并且基于写信号来更新输出指针以指向输入寄存器中的有效数据。