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    Device for driving a memory cell of a memory module by means of a charge store
    2.
    发明授权
    Device for driving a memory cell of a memory module by means of a charge store 失效
    用于通过电荷存储器驱动存储器模块的存储单元的装置

    公开(公告)号：US07012843B2

    公开(公告)日：2006-03-14

    申请号：US10180818

    申请日：2002-06-26

    申请人： Peter Schroegmeier ,  Thilo Marx ,  Manfred Dobler

    发明人： Peter Schroegmeier ,  Thilo Marx ,  Manfred Dobler

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4085

    摘要： A device for driving a memory cell (601) of a memory module which can be operated with an external voltage (VEXT) and an operating frequency (fCLK), whereas the memory cell (601) has a capacitance (600) for storing charges and a transistor (602) for reading charges from the capacitance (600) and for writing charges to the capacitance (600), which transistor can be controlled with a control voltage (VPP), which has a charge store (614) for supplying a control voltage (VPP) which is greater than the external voltage (VEXT). The charge store (614) being able to be charged by the external voltage (VEXT), and the charging of the charge store (614) is able to be controlled by a charging control frequency (fCC) derived from the operating frequency (fCLK) of the memory module.

    摘要翻译： 一种用于驱动存储器模块的存储单元（601）的装置，其可以用外部电压（V OUT）和工作频率（f CLK）操作，而 存储单元（601）具有用于存储电荷的电容（600）和用于从电容（600）读取电荷并用于向电容（600）写入电荷的晶体管（602），该晶体管可以用控制电压 （V SUB PP）具有用于提供大于外部电压（V OUT）的控制电压（V SUB PP）的电荷存储器（614） / SUB>）。 电荷存储器（614）能够被外部电压（V OUT）充电，并且电荷存储器（614）的充电能够通过充电控制频率（f < 从存储器模块的工作频率（f CLK）导出的信号（SUB> CC ）。

    Integrated memory having column decoder for addressing corresponding bit line
    4.
    发明授权
    Integrated memory having column decoder for addressing corresponding bit line 失效
    具有用于寻址相应位线的列解码器的集成存储器

    公开(公告)号：US06188642B1

    公开(公告)日：2001-02-13

    申请号：US09348736

    申请日：1999-07-06

    申请人： Sabine Schöniger ,  Peter Schrögmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    发明人： Sabine Schöniger ,  Peter Schrögmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    IPC分类号： G11C800

    CPC分类号： G11C8/00

    摘要： The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.

    摘要翻译： 集成存储器具有用于解码列地址并用于寻址对应位线的列解码器。 存储器还具有第一列地址总线，其用于将第一列地址传送到列解码器，以及第二列地址总线，其用于将第二列地址传送到列解码器。 列解码器在每种情况下都对应于提供给它的第一列地址和第二列地址的位线。

    Integrated memory
    8.
    发明授权
    Integrated memory 有权
    集成内存

    公开(公告)号：US06101141A

    公开(公告)日：2000-08-08

    申请号：US344922

    申请日：1999-06-28

    申请人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    发明人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/02

    CPC分类号： G11C7/1048 ,  G11C11/4096 ,  G11C7/1006

    摘要： The integrated memory has a data line pair, which is connected to a bit line pair via at least one differential amplifier. In addition, it has a control unit for setting first potential states on the data line pair which correspond to the differential signals of data to be written to the memory cells, and for setting at least one second potential state on the data line pair which does not correspond to any datum to be written to the memory cells. Furthermore, it has a detector unit having two inputs connected to the data line pair. The detector unit initiates a specific control function when the second potential state of the data line pair occurs.

    摘要翻译： 集成存储器具有数据线对，其经由至少一个差分放大器连接到位线对。 此外，它具有控制单元，用于设置数据线对上对应于要写入存储单元的数据的差分信号的第一电位状态，并且在数据线对上设置至少一个第二电位状态 不对应于要写入存储单元的任何数据。 此外，它具有检测器单元，其具有连接到数据线对的两个输入。 当发生数据线对的第二电位状态时，检测器单元启动特定的控制功能。