公开(公告)号：US10664641B2

公开(公告)日：2020-05-26

申请号：US15933785

申请日：2018-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hiranmay Biswas ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Meng-Xiang Lee

IPC: G06F17/50 ,  G06F30/394 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528 ,  G06F111/04 ,  G06F111/20 ,  G06F119/18

Abstract: A method for forming an integrated device includes following operations. A first circuit is provided. The first circuit has a first connecting path, a plurality of second connecting paths, and a third connecting path. The plurality of second connecting paths are electrically connected to a first connecting portion of the first connecting path. The third connecting path is electrically coupled to a second connecting portion of the first connecting path. An electromigration (EM) data of the first connecting path is analyzed to determine if a third connecting portion between the first connecting portion and the second connecting portion induces EM phenomenon. The first circuit is modified for generating a second circuit when the third connecting portion induces EM phenomenon. The integrated device according to the second circuit is generated.

公开(公告)号：US10515178B2

公开(公告)日：2019-12-24

申请号：US15882188

申请日：2018-01-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hiranmay Biswas ,  Chung-Hsing Wang ,  Kuo-Nan Yang ,  Yi-Kan Cheng

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

Abstract: A method (of generating a layout diagram of a conductive line structure includes: determining that a first set of first to fourth short pillar patterns (which represent portions of an M(i) layer of metallization and are located relative to a grid), violates a minimum transverse-routing (TVR) distance of alpha-direction-separation, wherein (1) the grid has orthogonal alpha and beta tracks, and (2) the short pillar patterns have long axes which are substantially co-track aligned with a first one of the alpha tracks and have a first distance (of alpha-direction-separation between immediately adjacent members of the first set) which is less than the TVR distance; and merging pairings of the first & second and third & fourth short pillar patterns into corresponding first and second medium pillar patterns which have a second distance of alpha-direction-separation therebetween; the second value being greater than the TVR distance.

公开(公告)号：US10509886B2

公开(公告)日：2019-12-17

申请号：US15844313

申请日：2017-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chin-Shen Lin ,  Meng-Xiang Lee ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F17/50

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), the layout comprising a resistor-capacitor (RC) netlist comprising a plurality of circuit nodes; identifying an RC network in the RC netlist; determining a characterization matrix corresponding to the RC network; updating the RC netlist by replacing the RC network with the characterization matrix; and calculating voltages and currents of the plurality of circuit nodes based on the updated RC netlist.

公开(公告)号：US20180047716A1

公开(公告)日：2018-02-15

申请号：US15791320

申请日：2017-10-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L23/528 ,  H01L21/768 ,  H01L23/50 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L27/0207 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

公开(公告)号：US09799639B2

公开(公告)日：2017-10-24

申请号：US15070904

申请日：2016-03-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L27/06 ,  H01L23/528 ,  H01L23/50 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/324 ,  H01L23/532

CPC classification number: H01L27/0207 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

公开(公告)号：US09231106B2

公开(公告)日：2016-01-05

申请号：US13790814

申请日：2013-03-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Kuo-Nan Yang ,  Ming-Hsiang Song ,  Ta-Pen Guo

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/20 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7835 ,  H01L29/785

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.

Abstract translation: 本公开的实施例是半导体器件，FinFET器件和形成FinFET器件的方法。 实施例是一种半导体器件，包括在衬底上延伸的第一半导体鳍片，第一半导体鳍片上的第一源极区域和第一半导体鳍片上的第一漏极区域。 第一源区具有第一宽度，第一漏区具有第二宽度，第二宽度不同于第一宽度。

公开(公告)号：US20150348962A1

公开(公告)日：2015-12-03

申请号：US14470716

申请日：2014-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/06 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/324 ,  H01L27/02 ,  H01L23/50

CPC classification number: H01L27/0207 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

Abstract translation: 在本公开中描述了在多个有源器件层上形成功率门控单元和虚拟功率电路的机构的实施例。 电源门控单元和虚拟电源电路形成在单独的有源器件层上，以允许与电源连接的互连结构形成在与用于连接电源门控单元和虚拟电源电路的互连结构的单独级别上。 这种分离防止这两种类型的互连结构竞争相同的空间。 两种类型的互连结构的路由变得更加容易。 结果，互连结构的金属长度减小并且金属宽度增加。 减少金属长度和增加的金属宽度降低电阻，提高电阻 - 电容（RC）延迟和电气性能，并提高互连可靠性，如减少电迁移。

公开(公告)号：US09171926B2

公开(公告)日：2015-10-27

申请号：US14543991

申请日：2014-11-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC: H01L21/8236 ,  H01L29/66 ,  H01L27/02 ,  H01L27/118 ,  H01L27/07 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/11807

Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

Abstract translation: 集成电路包括第一和第二标准单元。 第一标准单元包括第一栅极电极和第一栅极电极下面的第一沟道区域。 第一通道区域具有第一通道掺杂浓度。 第二标准单元包括第二栅极电极和第二栅极电极下面的第二沟道区域。 第二沟道区具有第二沟道掺杂浓度。 虚拟栅极分别包括第一和第二标准单元中的前半部分和第二半部分。 第一半和第二半分别在第一标准单元和第二标准单元的边缘处并且彼此抵接。 虚拟通道由虚拟门重叠。 虚拟通道具有基本上等于第一通道掺杂浓度和第二通道掺杂浓度之和的第三通道掺杂浓度。

公开(公告)号：US20140252477A1

公开(公告)日：2014-09-11

申请号：US13790814

申请日：2013-03-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Kuo-Nan Yang ,  Ming-Hsiang Song ,  Ta-Pen Guo

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7835 ,  H01L29/785

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.

Abstract translation: 本公开的实施例是半导体器件，FinFET器件和形成FinFET器件的方法。 实施例是一种半导体器件，包括在衬底上延伸的第一半导体鳍片，第一半导体鳍片上的第一源极区域和第一半导体鳍片上的第一漏极区域。 第一源区具有第一宽度，第一漏区具有第二宽度，第二宽度不同于第一宽度。

公开(公告)号：US12107048B2

公开(公告)日：2024-10-01

申请号：US18156086

申请日：2023-01-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wan-Yu Lo ,  Chung-Hsing Wang ,  Chin-Shen Lin ,  Kuo-Nan Yang ,  Meng-Xiang Lee ,  Hao-Tien Kan ,  Jhih-Hong Ye

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/5226

Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.