公开(公告)号：US20210383972A1

公开(公告)日：2021-12-09

申请号：US17411416

申请日：2021-08-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Anderson Lin ,  Chun-Ren Cheng ,  Chi-Yuan Shih ,  Shih-Fen Huang ,  Yi-Chuan Teng ,  Yi Heng Tsai ,  You-Ru Lin ,  Yen-Wen Chen ,  Fu-Chun Huang ,  Fan Hu ,  Ching-Hui Lin ,  Yan-Jie Liao

IPC: H01G4/012 ,  H01G4/228 ,  H01G4/12 ,  H01L21/3213 ,  H01L21/311 ,  H01L49/02 ,  H01L41/113 ,  H01L41/083 ,  H01L41/047

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

公开(公告)号：US20210376100A1

公开(公告)日：2021-12-02

申请号：US17405307

申请日：2021-08-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US20200350311A1

公开(公告)日：2020-11-05

申请号：US16923925

申请日：2020-07-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Fu-Chun Huang ,  Ching-Hui Lin ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Alexander Kalnitsky

IPC: H01L27/07 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L49/02

Abstract: A method for manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. A second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.

公开(公告)号：US10205024B2

公开(公告)日：2019-02-12

申请号：US15017225

申请日：2016-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Kuang-Hsin Chen ,  Chih-Hsin Ko ,  Shih-Fen Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

公开(公告)号：US09810689B2

公开(公告)日：2017-11-07

申请号：US15581673

申请日：2017-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Yi-Hsien Chang

IPC: H01L51/05 ,  G01N27/414 ,  G01N33/543 ,  H01L29/78 ,  C12Q1/00 ,  H01L51/00 ,  H01L29/66

CPC classification number: G01N33/5438 ,  C12Q1/006 ,  G01N27/414 ,  G01N27/4145 ,  G01N27/4148 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7832 ,  H01L51/0093 ,  H01L51/0512

Abstract: Dual-gate ion-sensitive field effect transistors (ISFETs) for disease diagnostics are disclosed herein. An exemplary dual-gate ISFET includes a gate structure and a fluidic gate structure disposed over opposite surfaces of a device substrate. The gate structure is disposed over a channel region defined between a source region and a drain region in the device substrate. The fluidic gate structure includes a sensing well that is disposed over the channel region. The sensing well includes a sensing layer and an electrolyte solution. The electrolyte solution includes a constituent that can react with a product of an enzymatic reaction that occurs when an enzyme-modified detection mechanism detects an analyte. The sensing layer can react with a first ion generated from the enzymatic reaction and a second ion generated from a reaction between the product of the enzymatic reaction and the constituent, such that the dual-gate ISFET generates an enhanced electrical signal.

公开(公告)号：US20170227533A1

公开(公告)日：2017-08-10

申请号：US15581673

申请日：2017-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Yi-Hsien Chang

IPC: G01N33/543 ,  C12Q1/00 ,  G01N27/414 ,  H01L29/78

CPC classification number: G01N33/5438 ,  C12Q1/006 ,  G01N27/414 ,  G01N27/4145 ,  G01N27/4148 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7832 ,  H01L51/0093 ,  H01L51/0512

Abstract: Dual-gate ion-sensitive field effect transistors (ISFETs) for disease diagnostics are disclosed herein. An exemplary dual-gate ISFET includes a gate structure and a fluidic gate structure disposed over opposite surfaces of a device substrate. The gate structure is disposed over a channel region defined between a source region and a drain region in the device substrate. The fluidic gate structure includes a sensing well that is disposed over the channel region. The sensing well includes a sensing layer and an electrolyte solution. The electrolyte solution includes a constituent that can react with a product of an enzymatic reaction that occurs when an enzyme-modified detection mechanism detects an analyte. The sensing layer can react with a first ion generated from the enzymatic reaction and a second ion generated from a reaction between the product of the enzymatic reaction and the constituent, such that the dual-gate ISFET generates an enhanced electrical signal.