公开(公告)号：US20240339446A1

公开(公告)日：2024-10-10

申请号：US18297182

申请日：2023-04-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Ying Lai ,  Po-Chih Su ,  Ruey-Hsin Liu

IPC: H01L27/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01L21/823493 ,  H01L27/0296 ,  H01L29/0607 ,  H01L29/66689 ,  H01L29/7818 ,  H03K17/08104

Abstract: Damage to an LDMOS transistor from voltage overshoot in a power switching circuit operating at high switching speeds is prevented by embedding a diode under a drain region of the LDMOS transistor. The embedded diode is doped more heavily than a drift region of the LDMOS transistor and lowers a breakdown voltage of the LDMOS transistor.

公开(公告)号：US11967645B2

公开(公告)日：2024-04-23

申请号：US17390565

申请日：2021-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yogendra Yadav ,  Chi-Chih Chen ,  Ruey-Hsin Liu ,  Chih-Wen Yao

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L27/07

CPC classification number: H01L29/7823 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835 ,  H01L27/0733 ,  H01L29/0847

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a field plate, a gate electrode, and a first dielectric layer. The substrate has a top surface. The substrate includes a first drift region with a first conductivity type extending from the top surface of the substrate into the substrate, and includes a second drill region with the first conductivity type extending from the top surface of the substrate into the substrate and adjacent to the first drift region. The field plate is over the substrate. The gate electrode has a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate. The first dielectric layer is between the substrate and the field plate. The first portion of the gate electrode is overlapping with a boundary of the first drift region and the second drift region in the substrate.

公开(公告)号：US11923429B2

公开(公告)日：2024-03-05

申请号：US17405307

申请日：2021-08-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/4238 ,  H01L21/26513 ,  H01L21/28123 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/78 ,  H01L29/4916

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US11817396B2

公开(公告)日：2023-11-14

申请号：US17388437

申请日：2021-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L21/762 ,  H01L29/78 ,  H01L23/552 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L23/552 ,  H01L21/28518 ,  H01L21/762 ,  H01L29/66477 ,  H01L29/78

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

公开(公告)号：US20210376100A1

公开(公告)日：2021-12-02

申请号：US17405307

申请日：2021-08-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US10686032B2

公开(公告)日：2020-06-16

申请号：US15185735

申请日：2016-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/861 ,  H01L49/02 ,  H01L27/08 ,  H01L23/535 ,  H01L29/36 ,  H01L29/78

Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

公开(公告)号：US10510880B2

公开(公告)日：2019-12-17

申请号：US16160443

申请日：2018-10-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Po-Chih Su

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L21/02 ,  H01L21/266 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/417

Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

公开(公告)号：US10381259B2

公开(公告)日：2019-08-13

申请号：US15614030

申请日：2017-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Alex Kalnitsky ,  Chih-Wen Yao ,  Jun Cai ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

IPC: H01L21/265 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/10

Abstract: A method of fabricating a semiconductor structure includes forming an isolation feature in a substrate, removing a portion of the isolation feature and a portion of the substrate underneath the removed portion of the isolation feature to form a trench in the substrate, and forming a trapping feature around a bottom portion of the trench. A first sidewall and a second sidewall of the trench are in direct contact with the isolation feature, and a bottom surface of the trench is below a bottom surface of the isolation feature.

公开(公告)号：US10205024B2

公开(公告)日：2019-02-12

申请号：US15017225

申请日：2016-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Kuang-Hsin Chen ,  Chih-Hsin Ko ,  Shih-Fen Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

公开(公告)号：US10170589B2

公开(公告)日：2019-01-01

申请号：US15897652

申请日：2018-02-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chih Su ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chun-Wai Ng

IPC: H01L29/66 ,  H01L27/088 ,  H01L27/098 ,  H01L21/74 ,  H01L29/78 ,  H01L21/306 ,  H01L21/768 ,  H01L29/08 ,  H01L29/40 ,  H01L21/8234

Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via.