公开(公告)号：US09830964B2

公开(公告)日：2017-11-28

申请号：US13770280

申请日：2013-02-19

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/00 ,  G11C7/22 ,  G06F3/06 ,  G06F12/02 ,  G06F9/44 ,  G06F1/32 ,  G06F13/00 ,  G06F11/14 ,  G06F11/10 ,  G11C14/00

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: Individual first ones of a plurality of non-volatile logic element arrays are designated to restore first in response to entering a wakeup or restoration mode. These non-volatile logic element arrays include instructions for an order in which other non-volatile logic element arrays are to be restored next. So configured, the processing device can be set to have one or more NVL arrays restored first, which arrays are pre-configured to guide further wakeup of the device through directed restoration from particular NVL arrays. Certain NVL arrays can be skipped if the functions stored therein are not needed, and the order of restoration of others can be tailored to a particular wakeup time and power concern through restoration in parallel, serial, or combinations thereof.

公开(公告)号：US09711196B2

公开(公告)日：2017-07-18

申请号：US13770399

申请日：2013-02-19

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F3/06 ,  G06F1/32 ,  G11C7/22 ,  G06F12/02 ,  G06F9/44 ,  G06F13/00 ,  G06F11/14 ,  G06F11/10 ,  G11C14/00

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.

公开(公告)号：US09070575B2

公开(公告)日：2015-06-30

申请号：US13953476

申请日：2013-07-29

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  John A. Rodriguez ,  Huang-Chun Wen ,  Steven Craig Bartling

IPC: H01L21/02 ,  H01L27/08 ,  H01L27/115 ,  H01L29/92 ,  H01L49/02 ,  H01L27/06 ,  H01L27/02

CPC classification number: H01L27/0805 ,  H01L27/0207 ,  H01L27/06 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L29/92

Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

Abstract translation: 用于集成去耦电容器的铁电电容器结构等。 铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。 铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。 串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。

公开(公告)号：US20150061739A1

公开(公告)日：2015-03-05

申请号：US14311752

申请日：2014-06-23

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: H03K3/356

CPC classification number: H03K3/356008

Abstract: In an embodiment of the invention, a dual-port negative level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and the control signals SS and SSN. The signals CKT, CLKZ, RET, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口负电平敏感数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，保持控制信号RET为低电平时，数据通过时钟反相器进行时钟输入。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和控制信号SS和SSN。 信号CKT，CLKZ，RET，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。

公开(公告)号：US08797783B1

公开(公告)日：2014-08-05

申请号：US13753782

申请日：2013-01-30

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C11/00 ,  G11C11/22

CPC classification number: G11C11/221

Abstract: A system on chip (SoC) provides a memory array of nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit is coupled to the node Q and is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed.

Abstract translation: 片上系统（SoC）提供了非易失性位单元的存储器阵列。 每个位单元包括在第一板线和第二板线之间串联连接的两个铁电电容器，使得在两个铁电电容器之间形成节点Q。 第一板线和第二板线配置成在位单元未被访问时提供大致等于第一电压的电压。 钳位电路耦合到节点Q并且可操作以在不访问位单元的情况下将节点Q钳位到大致等于第一电压的电压。

公开(公告)号：US08792288B1

公开(公告)日：2014-07-29

申请号：US13753800

申请日：2013-01-30

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C7/22 ,  G11C29/08

CPC classification number: G11C29/36 ,  G11C7/12 ,  G11C7/20 ,  G11C11/419 ,  G11C2029/1204

Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits.

Abstract translation: 片上系统（SoC）提供非易失性存储器阵列，其配置为n行x位的位单元。 每个位单元被配置为存储一位数据。 存在m个位线，每个位线耦合到位单元的m列的相应一个。 存在m个写入驱动器，每个m个驱动器都耦合到m个位线中的对应的一个，其中m个驱动器各自包括写入一个电路和写入零电路。 响应于耦合到写入一个电路的第一控制信号并且响应于耦合到写入的第二控制信号将全零写入位单元行中，m个驱动器可操作以将所有的一个写入一行位单元 零电路。

公开(公告)号：US20140075225A1

公开(公告)日：2014-03-13

申请号：US13770280

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/32

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: Individual first ones of a plurality of non-volatile logic element arrays are designated to restore first in response to entering a wakeup or restoration mode. These non-volatile logic element arrays include instructions for an order in which other non-volatile logic element arrays are to be restored next. So configured, the processing device can be set to have one or more NVL arrays restored first, which arrays are pre-configured to guide further wakeup of the device through directed restoration from particular NVL arrays. Certain NVL arrays can be skipped if the functions stored therein are not needed, and the order of restoration of others can be tailored to a particular wakeup time and power concern through restoration in parallel, serial, or combinations thereof.

Abstract translation: 多个非易失性逻辑元件阵列中的单独的第一个被指定为响应于进入唤醒或恢复模式而首先恢复。 这些非易失性逻辑元件阵列包括用于下一步要恢复其它非易失性逻辑元件阵列的顺序的指令。 如此配置，处理设备可被设置为首先恢复一个或多个NVL阵列，这些阵列被预配置为通过从特定NVL阵列的定向恢复来引导设备进一步唤醒。 如果不需要存储在其中的功能，则可以跳过某些NVL阵列，并且通过并行，串行或其组合的恢复，可以针对特定的唤醒时间和功率需求来调整其他的恢复顺序。

公开(公告)号：US20140075089A1

公开(公告)日：2014-03-13

申请号：US13770368

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F12/02

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processing device is operated using a plurality of volatile storage elements. Data in the plurality of volatile storage elements is stored in a plurality of non-volatile logic element arrays. A primary logic circuit portion of individual ones of the plurality of volatile storage elements is powered by a first power domain, and a slave stage circuit portion of individual ones of the plurality of volatile storage elements is powered by a second power domain. During a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the first power domain is powered down and the second power domain is maintained. In a further approach, the plurality of non-volatile logic element arrays is powered by a third power domain, which is powered down during regular operation of the processing device.

Abstract translation: 使用多个易失性存储元件来操作处理装置。 多个易失性存储元件中的数据被存储在多个非易失性逻辑元件阵列中。 多个易失性存储元件中的各个易失性存储元件的主要逻辑电路部分由第一电源域供电，并且多个易失性存储元件中的单个的易失性存储元件的从属级电路部分由第二电源域供电。 在从多个非易失性逻辑单元阵列向多个易失性存储元件的数据写回期间，第一功率域被断电并维持第二功率域。 在另一种方法中，多个非易失性逻辑单元阵列由第三功率域供电，该第三功率域在处理设备的常规操作期间被关断。

公开(公告)号：US20140075088A1

公开(公告)日：2014-03-13

申请号：US13770304

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F3/06

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

Abstract translation: 使用多个易失性存储元件来操作处理装置。 每个组的多个易失性存储元件的N组M个易失性存储元件使用多路复用器连接到多个非易失性逻辑元件阵列的N×M个非易失性逻辑元件阵列。 多路复用器将N个组中的一个连接到N个M大小的非易失性逻辑单元阵列，以将来自M个易失性存储元件的数据一次存储为N个M大小的非易失性逻辑单元阵列的行或写入 数据一次从N个M大小的非易失性逻辑元件阵列的一行移动到M个易失性存储元件。 相应的非易失性逻辑控制器控制关于易失性存储元件和非易失性存储元件之间的连接的复用器操作。

公开(公告)号：US20130313679A1

公开(公告)日：2013-11-28

申请号：US13953476

申请日：2013-07-29

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  John A. Rodriguez ,  Huang-Chun Wen ,  Steven Craig Bartling

IPC: H01L27/08 ,  H01L27/06

CPC classification number: H01L27/0805 ,  H01L27/0207 ,  H01L27/06 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L29/92

Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

Abstract translation: 用于集成去耦电容器的铁电电容器结构等。 铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。 铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。 串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。