公开(公告)号：US11322221B2

公开(公告)日：2022-05-03

申请号：US17037674

申请日：2020-09-30

Applicant: Sharp Semiconductor Innovation Corporation ,  TOHOKU UNIVERSITY

Inventor： Shigeo Ohyama ,  Tetsuo Endoh

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/06 ,  G11C7/10

Abstract: A memory device includes: a memory cell capable of holding data; and an ECC circuit capable of generating a correction code and detecting an error based on the correction code. The memory cell is accessed by a pipeline operation. The pipeline operation includes at least four pipeline stages including a read cycle reading data from the memory cell, an ECC cycle executing generation of the correction code or error detection for the memory cell in the ECC circuit, a wait cycle during which processing for data related to the memory cell is not executed, and a write cycle writing data into the memory cell.

公开(公告)号：US11200933B2

公开(公告)日：2021-12-14

申请号：US16305649

申请日：2017-03-21

Applicant: TOHOKU UNIVERSITY

Inventor： Shunsuke Fukami ,  Chaoliang Zhang ,  Ayato Ohkawara ,  Kyota Watanabe ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C11/15 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: The magnetic memory element (100) includes: a conductive layer that includes a heavy metal layer (10) containing a 5d transition metal; a first ferromagnetic layer (20) that is adjacent to the conductive layer and contains a ferromagnetic layer having a reversible magnetization; a barrier layer (30) that is adjacent to the first ferromagnetic layer (20) and includes an insulating material; a reference layer (40) that is adjacent to the barrier layer (30) and has at least one second ferromagnetic layer (41) having a fixed magnetization direction; a cap layer (50) that is adjacent to the reference layer (40) and includes a conductive material; a first terminal (T1) that is capable of introducing a current into one end of the heavy metal layer (10) in the longitudinal direction; a second terminal (T2) that is capable of introducing a current into the other end of the heavy metal layer (10) in the longitudinal direction; and a third terminal (T3) that is capable of introducing a current into the cap layer (50).

公开(公告)号：US10998491B2

公开(公告)日：2021-05-04

申请号：US16971262

申请日：2019-02-06

Applicant: TOHOKU UNIVERSITY

Inventor： Kyota Watanabe ,  Shunsuke Fukami ,  Hideo Sato ,  Hideo Ohno ,  Tetsuo Endoh

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetoresistance effect element is provided, which can, even in a region where the element size of the magnetoresistance effect element is small, implement stable record holding at higher temperatures, and moreover which has higher thermal stability.
The magnetoresistance effect element has a configuration including reference layer (B1)/first non-magnetic layer (1)/first magnetic layer (21)/first non-magnetic insertion layer (31)/second magnetic layer (22). A magnetostatic coupling is established between the first magnetic layer (21) and the second magnetic layer (22) due to magnetostatic interaction becoming dominant.

公开(公告)号：US10783294B2

公开(公告)日：2020-09-22

申请号：US16323146

申请日：2017-08-03

Applicant: TOHOKU UNIVERSITY

Inventor： Masanori Natsui ,  Akira Tamakoshi ,  Takahiro Hanyu ,  Akira Mochizuki ,  Tetsuo Endoh ,  Hiroki Koike ,  Hideo Ohno

IPC: G06F17/50 ,  G06F30/327 ,  G06F30/00 ,  G06F30/398

Abstract: A circuit design support system, a circuit design support method, a circuit design support program, and a recording medium having the program recorded thereon are provided by which a design can be performed in consideration of the stochastic operation of the stochastic operation element and the influence caused by the stochastic operation of the stochastic operation element on the operation reliability of the circuit can be evaluated.

公开(公告)号：US20200265883A1

公开(公告)日：2020-08-20

申请号：US16647155

申请日：2014-09-14

Applicant: Tohoku University

Inventor： Takahiro Hanyu ,  Daisuke Suzuki ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C11/16

Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

公开(公告)号：US10749107B2

公开(公告)日：2020-08-18

申请号：US16320260

申请日：2017-03-17

Applicant: TOHOKU UNIVERSITY

Inventor： Hiroaki Honjo ,  Shoji Ikeda ,  Hideo Sato ,  Tetsuo Endoh ,  Hideo Ohno

IPC: H01L43/12 ,  C23C14/14 ,  C23C14/34 ,  H01L43/08 ,  H01L21/8239 ,  H01L27/105 ,  H01L27/22 ,  H01L43/10

Abstract: A magnetic tunnel junction element configured by stacking, in a following stack order, a fixed layer formed of a ferromagnetic body and in which a magnetization direction is fixed, a magnetic coupling layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body and in which the magnetization direction is fixed, a barrier layer formed of a nonmagnetic body, and a recording layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, and a recording layer formed by sandwiching an insertion layer formed of a nonmagnetic body between first and second ferromagnetic layers, wherein the magnetic coupling layer is formed using a sputtering gas in which a value of a ratio in which a mass number of an element used in the magnetic coupling layer divided by the mass number of the sputtering gas itself is 2.2 or smaller.

公开(公告)号：US10693449B2

公开(公告)日：2020-06-23

申请号：US16335421

申请日：2017-09-15

Applicant: Tohoku University

Inventor： Kazuki Itoh ,  Tetsuo Endoh

IPC: H02M3/158 ,  H03K17/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H02M1/08 ,  H02M1/00

Abstract: A switching circuit device includes high-side and low-side switching element circuits, and high-side and low-side drive circuits. The high-side switching element circuit includes a high-side switching element connected between an output terminal and a high-voltage terminal of a high voltage source. The low-side switching element circuit includes a low-side switching element connected between the output terminal and a reference potential terminal. The high-side drive circuit turns on the high-side switching element. The low-side drive circuit turns on the low-side switching element. The high-side drive circuit includes a bootstrap capacitor connected to a drive power source. The bootstrap capacitor is charged while the low-side switching element is ON. The high-side drive circuit applies a gate voltage to the high-side switching element while the low-side switching element is OFF. The gate voltage is defined by adding a voltage of the output terminal to a voltage of the bootstrap capacitor.

公开(公告)号：US20200168264A1

公开(公告)日：2020-05-28

申请号：US16485289

申请日：2018-02-13

Applicant: Tohoku University

Inventor： Tetsuo Endoh ,  Yasuhiro Ohtomo

IPC: G11C11/16 ,  G11C11/22 ,  G11C13/00

Abstract: A memory device includes a memory cell array in which plural memory cells are arranged in a matrix manner, and a mode selection part. The mode selection part has at least any two of a first mode, a second mode, a third mode and selects any operation mode. The first mode is for reading and writing 1-bit data with the first memory cell or the second memory cell. The second mode is for reading and writing the 1-bit data with a cell unit including the N first memory cells and the N second memory cells connected to a bit line pair. The third mode is for reading and writing the 1-bit data with a cell unit including the M first memory cells and the M second memory cells connected to the bit line pair. M and N are 1 or more integers which are different from each other.

公开(公告)号：US20190115430A1

公开(公告)日：2019-04-18

申请号：US16089421

申请日：2017-03-30

Applicant: Tohoku University

Inventor： Kunihiro Tsubomi ,  Tetsuo Endoh ,  Masakazu Muraguchi

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L21/76

Abstract: Provided is a semiconductor device. A semiconductor device includes a substrate, a buffer layer provided on the substrate, a semiconductor layer provided on the buffer layer, a body region provided at a part of a surface layer of the semiconductor layer, a source region provided at a part of a surface layer of the body region, a drain region provided at a part of the surface layer of the semiconductor layer outside the body region, a gate insulating layer provided to extend from the surface layer of the body region to a predetermined depth, a gate electrode provided on the gate insulating layer, a source electrode provided on the source region, a drain electrode provided on the drain region, and an isolation region provided to extend from the surface layer of the semiconductor layer to above the predetermined depth.

公开(公告)号：US10164174B2

公开(公告)日：2018-12-25

申请号：US15872922

申请日：2018-01-16

Applicant: TOHOKU UNIVERSITY

Inventor： Hideo Sato ,  Shoji Ikeda ,  Mathias Bersweiler ,  Hiroaki Honjo ,  Kyota Watanabe ,  Shunsuke Fukami ,  Fumihiro Matsukura ,  Kenchi Ito ,  Masaaki Niwa ,  Tetsuo Endoh ,  Hideo Ohno

IPC: H01L43/08 ,  H01F10/16 ,  H01F10/32 ,  H01L27/105 ,  H01L29/82 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10

Abstract: A magnetoresistance effect element includes first and second magnetic layers having a perpendicular magnetization direction, and a first non-magnetic layer disposed adjacent to the first magnetic layer and on a side opposite to a side on which the second magnetic layer is disposed. An interfacial perpendicular magnetic anisotropy exists at an interface between the first magnetic layer and the first non-magnetic layer, and the anisotropy causes the first magnetic layer to have a magnetization direction perpendicular to the surface if the layers. The second magnetic layer has a saturation magnetization lower than that of the first magnetic layer, and an interfacial magnetic anisotropy energy density (Ki) at the interface between the first magnetic layer and the first non-magnetic layer is greater than that of an interface between the first non-magnetic layer and second magnetic layers if being disposed adjacent each other.