公开(公告)号：US11715723B2

公开(公告)日：2023-08-01

申请号：US17186984

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768 ,  H01L21/304 ,  H01L21/306

CPC classification number: H01L24/94 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/76898 ,  H01L24/06 ,  H01L24/33 ,  H01L2224/03845 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/2784 ,  H01L2224/27831 ,  H01L2224/27845 ,  H01L2224/29005 ,  H01L2224/29011 ,  H01L2224/29016 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/83203 ,  H01L2224/83896 ,  H01L2224/9211 ,  H01L2225/06544

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

公开(公告)号：US20220375793A1

公开(公告)日：2022-11-24

申请号：US17874741

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L21/768 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00

Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.

公开(公告)号：US11502062B2

公开(公告)日：2022-11-15

申请号：US17334025

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Nien-Fang Wu

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522 ,  H01L23/00 ,  H01L23/544 ,  H01L23/528 ,  H01L25/00 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/78 ,  H01L21/683 ,  H01L23/48 ,  H01L21/66

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

公开(公告)号：US20220278074A1

公开(公告)日：2022-09-01

申请号：US17186984

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

公开(公告)号：US11282810B2

公开(公告)日：2022-03-22

申请号：US16923115

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683 ,  H01L23/544

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US11244896B2

公开(公告)日：2022-02-08

申请号：US16258652

申请日：2019-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Chien Hsiao ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chieh-Yen Chen

IPC: H01L23/522 ,  H01L29/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L29/739 ,  H01L23/66 ,  H01L21/56 ,  H01L21/683

Abstract: A package structure includes a die, an encapsulant, and a first redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes a ground plane within the die. The encapsulant encapsulates the die. The first redistribution structure is over the active surface of the die. The first redistribution structure includes an antenna pattern electrically coupled with the ground plane. The antenna pattern is electrically connected to the die.

公开(公告)号：US20210391322A1

公开(公告)日：2021-12-16

申请号：US16900996

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L27/06 ,  H01L23/538 ,  H01L21/78 ,  H01L21/768

Abstract: A package structure and a method of fabricating the same are provided. The method includes bonding a first die and a second die to a wafer in a first die region of the wafer hybrid bonding; bonding a first dummy structure to the wafer in the first die region and a first scribe line of the wafer; and singulating the wafer and the first dummy structure along the first scribe line to form a stacked integrated circuit (IC) structure.

公开(公告)号：US11114413B2

公开(公告)日：2021-09-07

申请号：US16581795

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L25/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/683

Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.

公开(公告)号：US11063022B2

公开(公告)日：2021-07-13

申请号：US16572622

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Hsien-Wei Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/544 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/304 ,  H01L27/12 ,  H01L21/683

Abstract: A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.

公开(公告)号：US20210082874A1

公开(公告)日：2021-03-18

申请号：US16572622

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Hsien-Wei Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/544 ,  H01L23/538 ,  H01L23/31 ,  H01L21/304 ,  H01L21/56 ,  H01L23/00

Abstract: A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.