公开(公告)号：US20200335349A1

公开(公告)日：2020-10-22

申请号：US16889448

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang LIN

IPC: H01L21/308 ,  H01L21/027 ,  G03F7/40 ,  G03F7/26

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.

公开(公告)号：US20200174380A1

公开(公告)日：2020-06-04

申请号：US16698044

申请日：2019-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting HUANG ,  Tung-Chin WU ,  Shih-Hsiang LO ,  Chih-Ming LAI ,  Jue-Chin YU ,  Ru-Gun LIU ,  Chin-Hsiang LIN

IPC: G03F7/20 ,  G06F16/23 ,  G06N3/04 ,  G06N3/08 ,  G06F30/392 ,  G06F30/398

Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.

公开(公告)号：US20200073238A1

公开(公告)日：2020-03-05

申请号：US16522135

申请日：2019-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： An-Ren ZI ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/004 ,  G03F7/038 ,  G03F7/039

Abstract: A photoresist composition comprises a polymer resin, a photoactive compound, an organometallic compound, an enhancement additive, and a first solvent. The enhancement additive is an ionic surfactant, a non-ionic surfactant, or a second solvent having a boiling point of greater than 150° C.

公开(公告)号：US20190384171A1

公开(公告)日：2019-12-19

申请号：US16197349

申请日：2018-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： An-Ren ZI ,  Chin-Hsiang LIN ,  Ching-Yu CHANG

IPC: G03F7/004 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/40 ,  G03F7/038 ,  G03F7/039 ,  H01L21/027

Abstract: A photoresist composition includes a photoresist material including metal oxide nanoparticles and a ligand, and an acid having an acid dissociation constant, pKa, of −15 pKa>9.

公开(公告)号：US20190155156A1

公开(公告)日：2019-05-23

申请号：US16021665

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren ZI ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/11 ,  H01L21/027 ,  G03F7/004 ,  G03F7/20 ,  G03F7/38 ,  G03F7/32 ,  G03F7/038 ,  G03F7/09 ,  H01L21/266 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a assist layer over the material layer. The assist layer includes a polymer backbone, an acid labile group (ALG) bonded to the polymer backbone, and a floating group bonded to the polymer backbone. The floating group includes carbon fluoride (CxFy). The method also includes forming a resist layer over the assist layer and patterning the resist layer.

公开(公告)号：US20190137883A1

公开(公告)日：2019-05-09

申请号：US16150789

申请日：2018-10-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Yen LIN ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/20 ,  H01L21/033 ,  H01L21/311 ,  G03F7/16

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The method includes exposing a portion of the resist layer by performing an exposure process. The resist layer includes a compound, and the compound has a carbon backbone, and a photoacid generator (PAG) group and/or a quencher group are bonded to the carbon backbone. The method also includes performing a baking process on the resist layer and etching a portion of the resist layer to form a patterned resist layer. The method includes patterning the material layer by using the patterned resist layer as a mask and removing the patterned resist layer.

公开(公告)号：US20190131290A1

公开(公告)日：2019-05-02

申请号：US15797842

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Wen CHO ,  Fu-Jye LIANG ,  Chun-Kuang CHEN ,  Chih-Tsung SHIH ,  Li-Jui CHEN ,  Po-Chung CHENG ,  Chin-Hsiang LIN

IPC: H01L27/02 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5009 ,  G06F17/5045 ,  G06F17/5068 ,  G06F2217/12 ,  H01L27/0203

Abstract: A layout modification method for fabricating an integrated circuit is provided. The layout modification method includes calculating uniformity of critical dimension of a patterned layer with a layout for an exposure manufacturing process to produce a semiconductor device. The patterned layer is divided into a first portion and a second portion which is adjacent to the first portion, and a width of the second portion equals to a penumbra size of the exposure manufacturing process. The layout modification method further includes retrieving an adjusting parameter for modifying the layout of the semiconductor device; determining a compensation amount based on the adjusting parameter and the uniformity of critical dimension; and compensating the critical dimension of the second portion of the patterned layer by utilizing the compensation amount to generate a modified layout.

公开(公告)号：US20190096675A1

公开(公告)日：2019-03-28

申请号：US16053463

申请日：2018-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren ZI ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: H01L21/266 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  G03F7/32

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The resist layer includes an inorganic material and an auxiliary. The inorganic material includes a plurality of metallic cores and a plurality of first linkers bonded to the metallic cores. The method includes exposing a portion of the resist layer. The resist layer includes an exposed region and an unexposed region. In the exposed region, the auxiliary reacts with the first linkers. The method also includes removing the unexposed region of the resist layer by using a developer to form a patterned resist layer. The developer includes a ketone-based solvent having a formula (a), wherein R1 is linear or branched C1-C5 alkyl, and R2 is linear or branched C3-C9 alkyl.

公开(公告)号：US20180337058A1

公开(公告)日：2018-11-22

申请号：US15599851

申请日：2017-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Han LAI ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: H01L21/308

CPC classification number: H01L21/3081 ,  B05D3/06 ,  B05D3/108 ,  C08L33/10 ,  C08L33/12 ,  C09D133/08 ,  C09D133/10 ,  C09D133/12 ,  C09D135/02 ,  G03F7/11 ,  H01L21/02318 ,  H01L21/02345 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/3086 ,  H01L21/3105

Abstract: Provided is a material composition and method for that includes providing a primer material including a surface interaction enhancement component, and a cross-linkable component. A cross-linking process is performed on the deposited primer material. The cross-linkable component self-cross-links in response to the cross-linking process to form a cross-linked primer material. The cross-lined primer material can protect an underlying layer while performing at least one process on the cross-linked primer material.

公开(公告)号：US20230065234A1

公开(公告)日：2023-03-02

申请号：US17459476

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pinyen LIN ,  Chin-Hsiang LIN ,  Huang-Lin CHAO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/3115

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.