公开(公告)号：US20230413544A1

公开(公告)日：2023-12-21

申请号：US18362092

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chun-Chieh Lu ,  Yu-Ming Lin

IPC: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C7/18 ,  H10B43/27 ,  H10B41/10 ,  H10B43/10 ,  G11C8/14

Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

公开(公告)号：US20230378334A1

公开(公告)日：2023-11-23

申请号：US18364964

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Tzu Ang Chao ,  Chao-Ching Cheng ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L27/092 ,  H01L29/24 ,  H01L29/417 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/8256 ,  H01L29/66 ,  H01L23/31 ,  H10K10/84 ,  H10K10/88 ,  H10K10/46 ,  H10K19/10 ,  H10K85/20

CPC classification number: H01L29/7606 ,  H01L27/092 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/45 ,  H01L29/78696 ,  H01L21/02568 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/47576 ,  H01L21/8256 ,  H01L29/66969 ,  H01L23/3171 ,  H10K10/84 ,  H10K10/88 ,  H10K10/466 ,  H10K10/484 ,  H10K19/10 ,  H10K85/221

Abstract: A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

公开(公告)号：US11695073B2

公开(公告)日：2023-07-04

申请号：US17072367

申请日：2020-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L29/78 ,  G11C11/22 ,  H01L29/24 ,  H01L29/786 ,  H01L29/04 ,  H01L29/66 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

CPC classification number: H01L29/78391 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

公开(公告)号：US11631698B2

公开(公告)日：2023-04-18

申请号：US17070536

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/11585 ,  H01L27/11578 ,  H01L27/11592 ,  H01L27/1159

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

公开(公告)号：US11527552B2

公开(公告)日：2022-12-13

申请号：US17130609

申请日：2020-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Mauricio Manfrini ,  Georgios Vellianitis

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11587 ,  H01L27/11585 ,  H01L29/66 ,  H01L29/51

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.

公开(公告)号：US20220352312A1

公开(公告)日：2022-11-03

申请号：US17813777

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Tzu-Ang Chao ,  Chun-Chieh Lu ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L29/06 ,  H01L51/05 ,  H01L51/00 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/423

Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

公开(公告)号：US20220123003A1

公开(公告)日：2022-04-21

申请号：US17076505

申请日：2020-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chun-Chieh Lu ,  Yu-Ming Lin

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  G11C7/18 ,  G11C8/14

Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

公开(公告)号：US20210399136A1

公开(公告)日：2021-12-23

申请号：US17123982

申请日：2020-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Mauricio Manfrini

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/49 ,  H01L21/447 ,  H01L21/383

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate layer, a low-doping semiconductor layer, a crystalline ferroelectric layer and source and drain terminals. The crystalline ferroelectric layer is disposed between the gate layer and the low-doping semiconductor layer. The source terminal and the drain terminal are disposed on the low-doping semiconductor layer.

公开(公告)号：US20210376153A1

公开(公告)日：2021-12-02

申请号：US17072367

申请日：2020-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/786 ,  H01L29/04 ,  H01L29/66 ,  H01L29/24

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

公开(公告)号：US11004965B2

公开(公告)日：2021-05-11

申请号：US16573892

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Hung-Li Chiang ,  Chun-Chieh Lu ,  Ming-Yang Li ,  Tzu-Chiang Chen

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/04 ,  H01L29/66 ,  H01L29/20 ,  H01L29/45

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.