公开(公告)号：US10546755B2

公开(公告)日：2020-01-28

申请号：US16129741

申请日：2018-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L27/088 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes: an isolation insulating layer; fin structures protruding from the isolation insulating layer; gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate; a first source/drain epitaxial layer and a second source/drain epitaxial layer disposed between two adjacent gate structures; and a first conductive contact disposed on the first source/drain epitaxial layer, and a second conductive contact disposed on the second source/drain epitaxial layer; a separation isolation region disposed between the first and second conductive contact; and an insulating layer disposed between the separation isolation region and the isolation insulating layer. The separation isolation region is made of a different material than the insulating layer.

公开(公告)号：US20190164842A1

公开(公告)日：2019-05-30

申请号：US16242720

申请日：2019-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.

公开(公告)号：US20190157269A1

公开(公告)日：2019-05-23

申请号：US15867058

申请日：2018-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L27/092 ,  H01L23/485 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/4757 ,  H01L21/311 ,  H01L21/302 ,  H01L21/768

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiments, the method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, a first source/drain (S/D) feature comprising silicon adjacent to the first gate structure, a second S/D feature comprising silicon germanium (SiGe) adjacent to the second gate structure; and one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features. The method further includes etching the one or more dielectric layers to form openings exposing the first and second S/D features, forming a masking layer over the first S/D feature, implanting gallium (Ga) into the second S/D feature while the masking layer is over the first S/D feature, removing the masking layer; and etching the first and second S/D features with an oxygen-atom-containing etchant.

公开(公告)号：US20190067130A1

公开(公告)日：2019-02-28

申请号：US15686698

申请日：2017-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  I-Wen Wu ,  Fu-Kai Yang ,  Jia-Heng Wang ,  Mei-Yun Wang

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/324 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/45 ,  H01L29/78 ,  H01L23/535 ,  H01L27/092

Abstract: A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first and second S/D features; and a second dielectric layer over the first dielectric layer. The first and second S/D features are adjacent to the first and second gate structures respectively. The first and second S/D features comprise different materials. The method further includes etching the first and second dielectric layers to expose the first and second S/D features; doping a p-type dopant to the first and second S/D features; and performing a selective etching process to the first and second S/D features after the doping of the p-type dopant. The selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.

公开(公告)号：US10177038B1

公开(公告)日：2019-01-08

申请号：US15882905

申请日：2018-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC: H01L21/8239 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L23/522 ,  H01L23/528

Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.

公开(公告)号：US09231098B2

公开(公告)日：2016-01-05

申请号：US14067154

申请日：2013-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tien-Chun Wang ,  Yi-Chun Lo ,  Chia-Der Chang ,  Guo-Chiang Chi ,  Chia-Ping Lo ,  Fu-Kai Yang ,  Hung-Chang Hsu ,  Mei-Yun Wang

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3115

CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7848

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括半导体衬底。 在半导体衬底中形成源极区和漏极区，并且在源极区和漏极区分别形成金属硅化物区。 半导体器件还包括形成在半导体衬底上并且在源极区域和漏极区域之间的金属栅极叠层。 半导体器件还包括形成在半导体衬底上并围绕金属栅堆叠的绝缘层，其中绝缘层具有分别暴露金属硅化物区域的接触开口。 半导体器件包括在接触开口的内壁上形成的电介质隔离衬垫层，其中整个电介质隔离衬垫层位于金属硅化物区域的正上方。 半导体器件包括形成在接触开口中的接触插塞。

公开(公告)号：US20250081523A1

公开(公告)日：2025-03-06

申请号：US18239283

申请日：2023-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Ming Lee ,  Shih-Chieh Wu ,  Po-Yu Huang ,  I-Wen Wu ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor die and the method of forming the same are provided. The semiconductor die includes a first interconnect structure, a second interconnect structure including a conductive feature, and a device layer between the first interconnect structure and the second interconnect structure. The device layer includes a semiconductor fin, a first gate structure on the semiconductor fin, a source/drain region adjacent the first gate structure, and a shared contact extending through the semiconductor fin to be electrically connected to the source/drain region and the first gate structure. The conductive feature contacts the shared contact.

公开(公告)号：US12166088B2

公开(公告)日：2024-12-10

申请号：US17854817

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting Fang ,  Chung-Hao Cai ,  Jui-Ping Lin ,  Chia-Hsien Yao ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/40 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

公开(公告)号：US20240379762A1

公开(公告)日：2024-11-14

申请号：US18779804

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chun-An Lin ,  Wei-Yuan Lu ,  Guan-Ren Wang ,  Peng Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

公开(公告)号：US20240332298A1

公开(公告)日：2024-10-03

申请号：US18738649

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/285 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/4757 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/485 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/02057 ,  H01L21/28525 ,  H01L21/302 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/47573 ,  H01L21/76801 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/485 ,  H01L27/0924 ,  H01L29/7848 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/665

Abstract: A semiconductor device includes a first transistor in a first region of a first conductivity type and a second transistor in a second region of a second conductivity type opposite to the first conductivity type. The first transistor includes a first gate stack, a first epitaxial feature in a source/drain (S/D) region of the first region, and a first metal silicide layer over the first epitaxial feature. The second transistor includes a second gate stack, a second epitaxial feature in an S/D region of the second region, a dopant-containing implant layer over the second epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant. A lowest point of a top surface of the first epitaxial feature is below a lowest point of a top surface of the second epitaxial feature.