公开(公告)号：US20210313230A1

公开(公告)日：2021-10-07

申请号：US17347332

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Jeng-Wei Yu ,  Li-Wei Chou ,  Tsz-Mei Kwok ,  Ming-Hua Yu

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/84 ,  H01L27/06

Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature over the first fin, a second lower semiconductor feature over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins. The semiconductor device also includes an upper semiconductor feature over and in physical contact with the first and second lower semiconductor features, and a dielectric layer on sidewalls of the first and second lower semiconductor features.

公开(公告)号：US20210057552A1

公开(公告)日：2021-02-25

申请号：US17092838

申请日：2020-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Ming-Hua Yu

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/36

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

公开(公告)号：US20200075597A1

公开(公告)日：2020-03-05

申请号：US16669595

申请日：2019-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Tsz-Mei Kwok ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/165 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/306

Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; two first fins in an N-type region of the semiconductor device; and two second fins in a P-type region of the semiconductor device. Each of the two first fins has a channel region and two source/drain (S/D) regions sandwiching the channel region. The semiconductor device further includes a gate stack engaging the channel regions of the two first fins; and four S/D features over the S/D regions of the two first fins. Each of the four S/D features includes a lower portion and an upper portion over the lower portion. Each of the lower portions of the four S/D features has a cross-sectional profile that is wider at its bottom than at its top. The upper portions of the four S/D features merge into two merged S/D features with one on each side of the gate stack.

公开(公告)号：US10546784B2

公开(公告)日：2020-01-28

申请号：US16049971

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Jeng-Wei Yu ,  Li-Wei Chou ,  Tsz-Mei Kwok ,  Ming-Hua Yu

IPC: H01L27/088 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/84 ,  H01L27/06

Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.

公开(公告)号：US10453925B2

公开(公告)日：2019-10-22

申请号：US15089153

申请日：2016-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tetsuji Ueno ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L29/00 ,  H01L29/167 ,  H01L21/02 ,  C23C16/02 ,  C30B25/18 ,  C30B29/06 ,  C23C16/44 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

公开(公告)号：US10164096B2

公开(公告)日：2018-12-25

申请号：US14833022

申请日：2015-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kun-Mu Li ,  Ming-Hua Yu ,  Tsz-Mei Kwok ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/84 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/12 ,  H01L29/66 ,  H01L29/165

Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

公开(公告)号：US09825036B2

公开(公告)日：2017-11-21

申请号：US15051072

申请日：2016-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Tsz-Mei Kwok ,  Ming-Hua Yu

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165 ,  H01L27/092 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device comprises a substrate; an isolation structure over the substrate; two fins extending from the substrate and through the isolation structure; a gate stack engaging channel regions of the two fins; a dielectric layer disposed over the isolation structure and adjacent to S/D regions of the two fins; and four S/D features over the S/D regions of the two fins. Each of the four S/D features includes a lower portion and an upper portion over the lower portion. The lower portions of the four S/D features are surrounded at least partially by the dielectric layer. The upper portions of the four S/D features merge into two merged second S/D features with one on each side of the gate stack. Each of the two merged S/D features has a curvy top surface.

公开(公告)号：US20170243868A1

公开(公告)日：2017-08-24

申请号：US15051072

申请日：2016-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Tsz-Mei Kwok ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L21/306 ,  H01L29/08 ,  H01L21/311 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device comprises a substrate; an isolation structure over the substrate; two fins extending from the substrate and through the isolation structure; a gate stack engaging channel regions of the two fins; a dielectric layer disposed over the isolation structure and adjacent to S/D regions of the two fins; and four S/D features over the S/D regions of the two fins. Each of the four S/D features includes a lower portion and an upper portion over the lower portion. The lower portions of the four S/D features are surrounded at least partially by the dielectric layer. The upper portions of the four S/D features merge into two merged second S/D features with one on each side of the gate stack. Each of the two merged S/D features has a curvy top surface.

公开(公告)号：US12062710B2

公开(公告)日：2024-08-13

申请号：US18361391

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Ming-Hua Yu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L29/78 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/49

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7851 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/4966

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

公开(公告)号：US12009427B2

公开(公告)日：2024-06-11

申请号：US17978027

申请日：2022-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kun-Mu Li ,  Tsz-Mei Kwok ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/3115 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/02255

Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.