公开(公告)号：US20210066119A1

公开(公告)日：2021-03-04

申请号：US16696272

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/84

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over a second well doped with a second-type dopant different from the first-type dopant. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

公开(公告)号：US20200343363A1

公开(公告)日：2020-10-29

申请号：US16397248

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Jhon Jhy Liaw ,  Kuo-Hua Pan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L27/088 ,  H01L21/02 ,  H01L21/768 ,  H01L21/762 ,  H01L21/308 ,  H01L21/8234

Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.

公开(公告)号：US10790184B2

公开(公告)日：2020-09-29

申请号：US16211949

申请日：2018-12-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Chun Lin ,  Tien-Shao Chuang ,  Kuang-Cheng Tai ,  Chun-Hung Chen ,  Chih-Hung Hsieh ,  Kuo-Hua Pan ,  Jhon-Jhy Liaw

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.

公开(公告)号：US20170084646A1

公开(公告)日：2017-03-23

申请号：US15364955

申请日：2016-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Jung-I Lin ,  Ta-Chun Lin ,  Tien-Lu Lin ,  Chen-Jong Wang

IPC: H01L27/146

CPC classification number: H01L21/764 ,  H01L21/76224 ,  H01L21/76227 ,  H01L21/76289 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/0921 ,  H01L27/1203 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L29/945

Abstract: A method for manufacturing an image sensor with deep trench spacing isolation is provided. A trench is formed in a semiconductor substrate, around and between a plurality of pixel regions of the semiconductor substrate. A cap is formed using epitaxy to seal a gap between sidewalls of the trench. Pixel sensors corresponding to the plurality of pixel regions are formed over or within the corresponding pixel regions. An image sensor resulting from the method is also provided.

公开(公告)号：US20160163749A1

公开(公告)日：2016-06-09

申请号：US14564196

申请日：2014-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Jung-I Lin ,  Ta-Chun Lin ,  Tien-Lu Lin ,  Chen-Jong Wang

IPC: H01L27/146

CPC classification number: H01L21/764 ,  H01L21/76224 ,  H01L21/76227 ,  H01L21/76289 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/0921 ,  H01L27/1203 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L29/945

Abstract: An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided.

Abstract translation: 提供了采用深沟槽间隔隔离的图像传感器。 多个像素传感器布置在半导体衬底之上或之内。 沟槽在多个像素传感器周围和相邻的像素传感器之间并且在半导体衬底中布置，并且沟槽在沟槽的侧壁之间具有间隙。 在覆盖间隙的位置处，在沟槽之上或之内布置盖。 盖子密封沟槽内的间隙。 还提供了一种制造图像传感器的方法。

公开(公告)号：US11791217B2

公开(公告)日：2023-10-17

申请号：US17246998

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/823462 ,  H01L21/31051 ,  H01L21/31105 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545

Abstract: A structure includes a fin on a substrate; first and second gate stacks over the fin and including first and second gate dielectric layers and first and second gate electrodes respectively; and a dielectric gate over the fin and between the first and second gate stacks. The dielectric gate includes a dielectric material layer on a third gate dielectric layer. In a cross-sectional view cut along a direction parallel to a lengthwise direction of the fin and offset from the fin, the first gate dielectric layer forms a first U shape, the third gate dielectric layer forms a second U shape, a portion of the first gate electrode is disposed within the first U shape, a portion of the dielectric material layer is disposed within the second U shape, and a portion of an interlayer dielectric layer is disposed laterally between the first and the second U shapes.

公开(公告)号：US20230145984A1

公开(公告)日：2023-05-11

申请号：US18149242

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L29/66795 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/02603 ,  H01L21/823431

Abstract: A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure

公开(公告)号：US20230101278A1

公开(公告)日：2023-03-30

申请号：US18062760

申请日：2022-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L21/764 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/786

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

公开(公告)号：US11532502B2

公开(公告)日：2022-12-20

申请号：US17150725

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L21/764 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/786

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

公开(公告)号：US20220246613A1

公开(公告)日：2022-08-04

申请号：US17728243

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768

Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.