公开(公告)号：US11211496B2

公开(公告)日：2021-12-28

申请号：US16937010

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xi-Zong Chen ,  Te-Chih Hsiung ,  Cha-Hsin Chao ,  Yi-Wei Chiu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/311 ,  H01L21/027 ,  H01L29/08 ,  H01L23/535

Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

公开(公告)号：US20210327742A1

公开(公告)日：2021-10-21

申请号：US17360157

申请日：2021-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Huei Chiu ,  Tsung Fan Yin ,  Chen-Yi Liu ,  Hua-Li Hung ,  Xi-Zong Chen ,  Yi-Wei Chiu

IPC: H01L21/683 ,  H01L21/67 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/687 ,  H01L21/768 ,  H01L29/78

Abstract: Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.

公开(公告)号：US11022878B2

公开(公告)日：2021-06-01

申请号：US16657551

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xi-Zong Chen ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Chih-Hsuan Lin

IPC: H01L21/033 ,  G03F7/004 ,  G03F7/20 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027

Abstract: The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.

公开(公告)号：US10707123B2

公开(公告)日：2020-07-07

申请号：US15725972

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Allen Ke ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Yu-Wei Kuo

IPC: H01L21/768 ,  H01L21/74 ,  H01L21/48 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

公开(公告)号：US10566232B2

公开(公告)日：2020-02-18

申请号：US15653368

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Jhih Shen ,  Yi-Wei Chiu ,  Hung Jui Chang

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/285

Abstract: Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.

公开(公告)号：US10510875B2

公开(公告)日：2019-12-17

申请号：US16000689

申请日：2018-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

公开(公告)号：US10290547B2

公开(公告)日：2019-05-14

申请号：US15823134

申请日：2017-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/311 ,  H01L29/78 ,  H01L27/088

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a conductive material in gate spaces created by removing portions of a dummy gate structure. The first layer further includes a top layer on an entire structure formed on a fin structure, and a gate space for a short channel gate and a gate space for a long channel gate. A first portion of the top layer is removed to leave a hard mask layer over a long channel gate region. The hard mask layer and a portion of heights of the conductive material in the gate spaces are removed to form a first structure. A second layer of the conductive material is formed over the first structure. Portions of the second layer are removed to create a recessed conductive portion for the short channel gate and a recessed conductive portion for the long channel gate.

公开(公告)号：US20190035908A1

公开(公告)日：2019-01-31

申请号：US16000689

申请日：2018-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/306 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

公开(公告)号：US10157782B2

公开(公告)日：2018-12-18

申请号：US15878883

申请日：2018-01-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jeng Chang Her ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC: H01L23/52 ,  H01L21/768 ,  H01L21/3115 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02

Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

公开(公告)号：US10083863B1

公开(公告)日：2018-09-25

申请号：US15684257

申请日：2017-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yu Hsieh ,  Jeng Chang Her ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC: H01L21/4763 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L21/76895 ,  H01L21/31116 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.