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    Pre-colored methodology of multiple patterning
    41.
    发明授权
    Pre-colored methodology of multiple patterning 有权
    多色图案的预色方法

    公开(公告)号：US09075936B2

    公开(公告)日：2015-07-07

    申请号：US14076566

    申请日：2013-11-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Huei Chen ,  Wei Min Chan ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G06F17/5068 ,  G06F2217/12

    Abstract: Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced.

    Abstract translation: 一些实施例涉及用于在集成芯片布局内预先着色数据的方法，以避免在多次图案化光刻期间由掩模未对准而产生的重叠误差。 该方法可以通过生成包含具有多个IC形状的集成芯片布局的图形IC布局文件来执行。 图形IC布局文件中的IC形状在分解过程中会分配一种颜色。 IC形状进一步预先着色，以故意将预色数据分配给相同的掩码。 在掩模建立过程中，与预先着色的IC形状相关联的数据将自动发送到相同的掩码，而不管分配给形状的颜色如何。 因此，预先着色的形状不是基于分解而分配给掩蔽的，而是基于预着色。 通过预先着色将IC形状分配给相同的掩模，可以减少重叠错误。

    WORDLINE TRACKING FOR BOOSTED-WORDLINE TIMING SCHEME
    42.
    发明申请
    WORDLINE TRACKING FOR BOOSTED-WORDLINE TIMING SCHEME 有权
    WORDLINE跟踪增强型WORDLINE时序方案

    公开(公告)号：US20140119101A1

    公开(公告)日：2014-05-01

    申请号：US13665031

    申请日：2012-10-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

    Inventor： Li-Wen Wang ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

    IPC: G11C8/08

    CPC classification number: G11C8/08 ,  G11C7/00 ,  G11C8/00 ,  G11C11/4063 ,  G11C16/04 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1202

    Abstract: Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells. A boost enable signal is provided. The state of the boost enable signal is indicative of whether the wordline voltage at a predetermined position on the wordline has reached a non-zero, predetermined wordline voltage. The wordline voltage is selectively boosted to a boosted wordline voltage level based on the boost enable signal.

    Abstract translation: 本公开的一些方面是一种方法。 在该方法中，字线电压被提供给字线，该字线耦合到多个存储器单元。 提供升压使能信号。 升压使能信号的状态表示字线上的预定位置的字线电压是否达到非零预定字线电压。 基于升压使能信号，字线电压被选择性地升压到升压的字线电压电平。

    SRAM cell word line structure with reduced RC effects
    43.
    发明授权
    SRAM cell word line structure with reduced RC effects 有权

    公开(公告)号：US12245412B2

    公开(公告)日：2025-03-04

    申请号：US18362786

    申请日：2023-07-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hidehiro Fujiwara ,  Wei-Min Chan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

    IPC: H10B10/00 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02

    Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

    Memory device with strap cells
    46.
    发明授权
    Memory device with strap cells 有权

    公开(公告)号：US11514952B2

    公开(公告)日：2022-11-29

    申请号：US17214560

    申请日：2021-03-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jonathan Tsung-Yung Chang ,  Cheng-Hung Lee ,  Chi-Ting Cheng ,  Hung-Jen Liao ,  Jhon-Jhy Liaw ,  Yen-Huei Chen

    IPC: G11C5/02 ,  G11C5/14 ,  G11C7/10 ,  G11C7/12 ,  G11C11/417 ,  G11C7/22

    Abstract: A device disclosed includes first and second rows of memory cells, a first data line, and a first continuous data line. The first and second rows of memory cells are arranged in a first sub-bank and a second sub-bank, separated from the first sub-bank, respectively. The first data line is arranged across the first sub-bank and coupled to a first memory cell in the first row of memory cells. The first continuous data line includes a first portion arranged across the first sub-bank and a second portion arranged across the second sub-bank. The first continuous data line is coupled to a second memory cell in the second row of memory cells. The first portion of the first continuous data line is disposed in a first metal layer. The first data line and the second portion of the first continuous data line are in a second metal layer.

    POWER SWITCH CONTROL FOR DUAL POWER SUPPLY
    49.
    发明申请
    POWER SWITCH CONTROL FOR DUAL POWER SUPPLY 审中-公开

    公开(公告)号：US20200020363A1

    公开(公告)日：2020-01-16

    申请号：US16582029

    申请日：2019-09-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

    IPC: G11C5/14 ,  H03K17/22 ,  H03K17/687

    Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

    POWER SWITCH CONTROL FOR DUAL POWER SUPPLY
    50.
    发明申请
    POWER SWITCH CONTROL FOR DUAL POWER SUPPLY 审中-公开

    公开(公告)号：US20190005990A1

    公开(公告)日：2019-01-03

    申请号：US15902118

    申请日：2018-02-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

    IPC: G11C5/14 ,  H03K17/687

    Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

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