公开(公告)号：US20210202238A1

公开(公告)日：2021-07-01

申请号：US16907634

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Hong-Jie Yang ,  Chia-Ying Lee ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/027 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L29/78

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

公开(公告)号：US11031500B2

公开(公告)日：2021-06-08

申请号：US16287368

申请日：2019-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang ,  Chun-Ming Yang ,  Yu-Chi Pan

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/285 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/49

Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

公开(公告)号：US20210134660A1

公开(公告)日：2021-05-06

申请号：US16906615

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US10283417B1

公开(公告)日：2019-05-07

申请号：US15833721

申请日：2017-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02

Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a semiconductor device includes a first gate structure and a second gate structure on a substrate; wherein the first gate structure includes a first gate dielectric layer having a first material, and the second gate structure includes a second gate dielectric layer having a second material, the first material being different from the second material, wherein the first and the second gate structures further includes a first and a second self-protective layers disposed on the first and the second gate dielectric layers respectively, wherein the first self-protective layer includes metal phosphate and the second self-protective layer includes boron including complex agents and a first work function tuning layer on the first self-protective layer in the first gate structure.

公开(公告)号：US20250056823A1

公开(公告)日：2025-02-13

申请号：US18931886

申请日：2024-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chun-Hsiang Fan ,  Yu-Wen Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/66 ,  H01L21/762 ,  H01L21/8238

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

公开(公告)号：US12136566B2

公开(公告)日：2024-11-05

申请号：US17969396

申请日：2022-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US20240313114A1

公开(公告)日：2024-09-19

申请号：US18673615

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US12051753B2

公开(公告)日：2024-07-30

申请号：US17852755

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US20240203740A1

公开(公告)日：2024-06-20

申请号：US18427512

申请日：2024-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28247 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32134 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66795 ,  H01L21/28079

Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.

公开(公告)号：US11923201B2

公开(公告)日：2024-03-05

申请号：US17187176

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28247 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32134 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66795 ,  H01L21/28079

Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.